I2C controller basics in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this I2C start condition process?

Consider the following VHDL process that generates an I2C start condition on SDA and SCL lines. What will be the value of SDA and SCL signals after the process completes?

VHDL

process
  begin
    SCL <= '1';
    SDA <= '1';
    wait for 10 ns;
    SDA <= '0'; -- Start condition: SDA goes low while SCL is high
    wait for 10 ns;
    SCL <= '0';
    wait;
  end process;

A SCL = '0', SDA = '0'

B SCL = '1', SDA = '0'

C SCL = '0', SDA = '1'

D SCL = '1', SDA = '1'

💡 Hint

Remember the I2C start condition requires SDA to go low while SCL is high, then SCL goes low.

The process sets SCL and SDA high initially, then pulls SDA low while SCL is still high to create the start condition. Finally, SCL is pulled low. So the final values are SCL='0' and SDA='0'.

🧠 Conceptual

intermediate

Which signal transition defines the I2C stop condition?

In I2C communication, the stop condition is a specific change on the SDA and SCL lines. Which of the following correctly describes the stop condition?

A SCL goes from high to low while SDA is high

B SDA goes from high to low while SCL is low

C SDA goes from low to high while SCL is high

D SCL goes from low to high while SDA is low

💡 Hint

Think about how the stop condition signals the end of communication by releasing the bus.

The stop condition occurs when SDA transitions from low to high while SCL is high, signaling the end of the data transfer.

🔧 Debug

advanced

Why does this VHDL code fail to generate a proper I2C clock?

Examine the following VHDL code snippet intended to generate a 100 kHz I2C clock on SCL. Identify the reason it does not produce the correct clock signal.

VHDL

process
  begin
    SCL <= '0';
    wait for 5 us;
    SCL <= '1';
    wait for 5 us;
  end process;

A The wait times are too short for 100 kHz frequency

B The process lacks a loop, so it runs only once and stops

C SCL signal is not declared as std_logic

D The process uses blocking assignments instead of non-blocking

💡 Hint

Consider how VHDL processes behave without loops or sensitivity lists.

Without a loop, the process executes once and then stops, so the clock toggling happens only once instead of continuously.

📝 Syntax

advanced

Which VHDL code correctly implements an I2C SDA line release (open-drain behavior)?

In I2C, the SDA line is open-drain and should be driven low or released (high impedance). Which code snippet correctly models releasing the SDA line in VHDL?

A SDA <= 'Z';

B SDA <= '1';

C SDA <= 'H';

D SDA <= '0';

💡 Hint

Open-drain means the line is not driven high but left floating (high impedance).

Assigning 'Z' to SDA releases the line, allowing the pull-up resistor to pull it high, which models open-drain behavior.

🚀 Application

expert

How many clock pulses are generated by this I2C bit transmission process?

Given the following VHDL process that transmits 8 bits over I2C by toggling SCL, how many rising edges of SCL occur during the transmission?

VHDL

process
  variable i : integer := 0;
  begin
    for i in 0 to 7 loop
      SDA <= data(i);
      SCL <= '0';
      wait for 5 us;
      SCL <= '1'; -- Rising edge
      wait for 5 us;
    end loop;
    wait;
  end process;

A 16

B 7

C 9

D 8

💡 Hint

Count how many times SCL goes from '0' to '1' inside the loop.

The loop runs 8 times, and each iteration generates one rising edge of SCL, so total 8 rising edges.

Practice

1. What are the two main signals controlled by an I2C controller in VHDL?

easy

A. CLK and RESET

B. TX and RX

C. MOSI and MISO

D. SCL (clock) and SDA (data)

Solution

1. Step 1: Understand I2C communication basics

   I2C uses two wires: one for clock (SCL) and one for data (SDA).

2. Step 2: Identify signals controlled by the controller

   The I2C controller manages these two lines to send and receive data.

3. Final Answer:

   SCL (clock) and SDA (data) -> Option D

4. Quick Check:

   I2C signals = SCL and SDA [OK]

Hint: Remember: I2C always uses clock and data lines [OK]

Common Mistakes:

• Confusing I2C signals with SPI signals
• Thinking TX/RX are used in I2C
• Mixing up clock and reset signals

2. Which VHDL statement correctly declares the SDA line as an output signal in an I2C controller?

easy

A. signal SDA : out std_logic;

B. signal SDA : in std_logic;

C. signal SDA : buffer std_logic;

D. signal SDA : inout std_logic;

Solution

1. Step 1: Recall VHDL signal directions

   Output signals are declared with the keyword 'out'.

2. Step 2: Match SDA line direction

   SDA is controlled by the I2C controller to send data, so it must be 'out'.

3. Final Answer:

   signal SDA : out std_logic; -> Option A

4. Quick Check:

   Output signal = 'out' [OK]

Hint: Output signals use 'out' keyword in VHDL [OK]

Common Mistakes:

• Using 'in' instead of 'out' for output signals
• Confusing 'buffer' and 'out' keywords
• Using 'inout' when only output is needed

3. Given this VHDL snippet for generating a start condition in I2C, what is the value of SDA after execution?

process(clk)
begin
  if rising_edge(clk) then
    SDA <= '1';
    SCL <= '1';
    SDA <= '0'; -- start condition
  end if;
end process;

medium

A. '1'

B. '0'

C. Undefined (multiple assignments in one clock)

D. Remains previous value

Solution

1. Step 1: Analyze signal assignments in process

   Within the same clock edge, SDA is first set to '1', then immediately to '0'.

2. Step 2: Understand signal assignment behavior in VHDL

   Last assignment in the process overrides previous ones, so SDA becomes '0'.

3. Final Answer:

   '0' -> Option B

4. Quick Check:

   Last assignment wins = '0' [OK]

Hint: Last signal assignment in process sets final value [OK]

Common Mistakes:

• Assuming first assignment sticks
• Thinking multiple assignments cause error
• Ignoring VHDL signal update rules

4. Identify the error in this VHDL code snippet for generating a stop condition in I2C:

process(clk)
begin
  if rising_edge(clk) then
    SDA <= '0';
    SCL <= '1';
    SDA <= '1'; -- stop condition
  end if;
end process;

medium

A. SDA should be set to '1' before SCL is '1'

B. No error, code is correct

C. Multiple assignments to SDA in one clock cause conflict

D. Stop condition requires SDA to go low, not high

Solution

1. Step 1: Review SDA assignments in the process

   SDA is assigned '0' then '1' in the same clock cycle.

2. Step 2: Understand VHDL signal assignment rules

   Multiple assignments to the same signal in one clock can cause unexpected behavior or synthesis issues.

3. Final Answer:

   Multiple assignments to SDA in one clock cause conflict -> Option C

4. Quick Check:

   Multiple assignments = conflict [OK]

Hint: Avoid multiple assignments to same signal in one clock [OK]

Common Mistakes:

• Ignoring multiple assignments problem
• Confusing start and stop condition logic
• Assuming code runs without synthesis warnings

5. You want to design an I2C controller in VHDL that sends a start condition, then transmits 8 bits of data, and finally sends a stop condition. Which sequence of signal changes correctly represents this process?

hard

A. SDA goes from high to low while SCL is high (start), then data bits sent on SDA with SCL toggling, then SDA goes low to high while SCL is high (stop)

B. SDA goes low to high while SCL is low (start), then data bits sent on SDA with SCL low, then SDA goes high to low while SCL is low (stop)

C. SCL stays low throughout, SDA toggles for start, data, and stop

D. SDA and SCL both toggle randomly during start, data, and stop

Solution

1. Step 1: Recall I2C start and stop conditions

   Start condition: SDA falls from high to low while SCL is high. Stop condition: SDA rises from low to high while SCL is high.

2. Step 2: Understand data transmission timing

   Data bits are sent on SDA line while toggling SCL clock line to synchronize bits.

3. Step 3: Match sequence to options

   SDA goes from high to low while SCL is high (start), then data bits sent on SDA with SCL toggling, then SDA goes low to high while SCL is high (stop) correctly describes the start, data, and stop signal changes.

4. Final Answer:

   Start: SDA high to low while SCL high, data sent with SCL toggling, stop: SDA low to high while SCL high -> Option A

5. Quick Check:

   Start/stop conditions require SDA change while SCL high [OK]

Hint: Start/stop change SDA only when SCL is high [OK]

Common Mistakes:

• Changing SDA when SCL is low for start/stop
• Not toggling SCL during data bits
• Confusing start and stop signal directions