I2C controller basics in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the I2C clock line signal.

VHDL

signal scl : std_logic := [1];

Drag options to blanks, or click blank then click option'

A'1'

B'0'

C"1"

D"0"

Attempts:

3 left

💡 Hint

Common Mistakes

Using double quotes instead of single quotes for std_logic values.

Initializing SCL to '1' instead of '0'.

The I2C clock line (SCL) is usually initialized to logic low ('0') in VHDL.

2fill in blank

medium

Complete the code to define the I2C SDA line as an inout port.

VHDL

port (sda : [1] std_logic);

Drag options to blanks, or click blank then click option'

Ainout

Bin

Cout

Dbuffer

Attempts:

3 left

💡 Hint

Common Mistakes

Declaring SDA as only input or output, which restricts direction.

Using 'buffer' which is less flexible than 'inout' for bidirectional lines.

The SDA line in I2C is bidirectional, so it must be declared as inout.

3fill in blank

hard

Fix the error in the process sensitivity list for I2C clock generation.

VHDL

process([1])
begin
  -- clock generation logic
end process;

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Aclk

Bscl

Cclk, reset

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Leaving out reset from the sensitivity list.

Using only scl which is an output, not a triggering signal.

The process should be sensitive to both the main clock and reset signals to properly generate the I2C clock.

4fill in blank

hard

Fill both blanks to complete the I2C start condition detection logic.

VHDL

if sda [1] '1' and scl [2] '1' then
  start_condition <= '1';
else
  start_condition <= '0';
end if;

Drag options to blanks, or click blank then click option'

A=

B/=

C<=

D>=

Attempts:

3 left

💡 Hint

Common Mistakes

Using inequality operators which would detect the wrong condition.

Using assignment operators instead of comparison.

The start condition occurs when both SDA and SCL lines are high, so we check if they are equal to '1'.

5fill in blank

hard

Fill all three blanks to complete the I2C address matching condition.

VHDL

if (address_reg [1] target_address) and (rw_bit [2] '0') and (ack [3] '1') then
  match <= '1';
else
  match <= '0';
end if;

Drag options to blanks, or click blank then click option'

A=

B/=

Cand

Dor

Attempts:

3 left

💡 Hint

Common Mistakes

Using inequality or logical OR which would cause incorrect matching.

Mixing assignment and comparison operators.

The address matches when the stored address equals the target, the read/write bit is '0' (write), and acknowledgment is '1'.

Practice

1. What are the two main signals controlled by an I2C controller in VHDL?

easy

A. CLK and RESET

B. TX and RX

C. MOSI and MISO

D. SCL (clock) and SDA (data)

Solution

1. Step 1: Understand I2C communication basics

   I2C uses two wires: one for clock (SCL) and one for data (SDA).

2. Step 2: Identify signals controlled by the controller

   The I2C controller manages these two lines to send and receive data.

3. Final Answer:

   SCL (clock) and SDA (data) -> Option D

4. Quick Check:

   I2C signals = SCL and SDA [OK]

Hint: Remember: I2C always uses clock and data lines [OK]

Common Mistakes:

• Confusing I2C signals with SPI signals
• Thinking TX/RX are used in I2C
• Mixing up clock and reset signals

2. Which VHDL statement correctly declares the SDA line as an output signal in an I2C controller?

easy

A. signal SDA : out std_logic;

B. signal SDA : in std_logic;

C. signal SDA : buffer std_logic;

D. signal SDA : inout std_logic;

Solution

1. Step 1: Recall VHDL signal directions

   Output signals are declared with the keyword 'out'.

2. Step 2: Match SDA line direction

   SDA is controlled by the I2C controller to send data, so it must be 'out'.

3. Final Answer:

   signal SDA : out std_logic; -> Option A

4. Quick Check:

   Output signal = 'out' [OK]

Hint: Output signals use 'out' keyword in VHDL [OK]

Common Mistakes:

• Using 'in' instead of 'out' for output signals
• Confusing 'buffer' and 'out' keywords
• Using 'inout' when only output is needed

3. Given this VHDL snippet for generating a start condition in I2C, what is the value of SDA after execution?

process(clk)
begin
  if rising_edge(clk) then
    SDA <= '1';
    SCL <= '1';
    SDA <= '0'; -- start condition
  end if;
end process;

medium

A. '1'

B. '0'

C. Undefined (multiple assignments in one clock)

D. Remains previous value

Solution

1. Step 1: Analyze signal assignments in process

   Within the same clock edge, SDA is first set to '1', then immediately to '0'.

2. Step 2: Understand signal assignment behavior in VHDL

   Last assignment in the process overrides previous ones, so SDA becomes '0'.

3. Final Answer:

   '0' -> Option B

4. Quick Check:

   Last assignment wins = '0' [OK]

Hint: Last signal assignment in process sets final value [OK]

Common Mistakes:

• Assuming first assignment sticks
• Thinking multiple assignments cause error
• Ignoring VHDL signal update rules

4. Identify the error in this VHDL code snippet for generating a stop condition in I2C:

process(clk)
begin
  if rising_edge(clk) then
    SDA <= '0';
    SCL <= '1';
    SDA <= '1'; -- stop condition
  end if;
end process;

medium

A. SDA should be set to '1' before SCL is '1'

B. No error, code is correct

C. Multiple assignments to SDA in one clock cause conflict

D. Stop condition requires SDA to go low, not high

Solution

1. Step 1: Review SDA assignments in the process

   SDA is assigned '0' then '1' in the same clock cycle.

2. Step 2: Understand VHDL signal assignment rules

   Multiple assignments to the same signal in one clock can cause unexpected behavior or synthesis issues.

3. Final Answer:

   Multiple assignments to SDA in one clock cause conflict -> Option C

4. Quick Check:

   Multiple assignments = conflict [OK]

Hint: Avoid multiple assignments to same signal in one clock [OK]

Common Mistakes:

• Ignoring multiple assignments problem
• Confusing start and stop condition logic
• Assuming code runs without synthesis warnings

5. You want to design an I2C controller in VHDL that sends a start condition, then transmits 8 bits of data, and finally sends a stop condition. Which sequence of signal changes correctly represents this process?

hard

A. SDA goes from high to low while SCL is high (start), then data bits sent on SDA with SCL toggling, then SDA goes low to high while SCL is high (stop)

B. SDA goes low to high while SCL is low (start), then data bits sent on SDA with SCL low, then SDA goes high to low while SCL is low (stop)

C. SCL stays low throughout, SDA toggles for start, data, and stop

D. SDA and SCL both toggle randomly during start, data, and stop

Solution

1. Step 1: Recall I2C start and stop conditions

   Start condition: SDA falls from high to low while SCL is high. Stop condition: SDA rises from low to high while SCL is high.

2. Step 2: Understand data transmission timing

   Data bits are sent on SDA line while toggling SCL clock line to synchronize bits.

3. Step 3: Match sequence to options

   SDA goes from high to low while SCL is high (start), then data bits sent on SDA with SCL toggling, then SDA goes low to high while SCL is high (stop) correctly describes the start, data, and stop signal changes.

4. Final Answer:

   Start: SDA high to low while SCL high, data sent with SCL toggling, stop: SDA low to high while SCL high -> Option A

5. Quick Check:

   Start/stop conditions require SDA change while SCL high [OK]

Hint: Start/stop change SDA only when SCL is high [OK]

Common Mistakes:

• Changing SDA when SCL is low for start/stop
• Not toggling SCL during data bits
• Confusing start and stop signal directions