I2C controller basics in VHDL - Mini Project: Build & Apply

I2C Controller Basics

📖 Scenario: You are designing a simple I2C controller in VHDL to communicate with an I2C device. The controller will generate the start condition, send a 7-bit address with a write bit, and then generate the stop condition.

🎯 Goal: Build a basic I2C controller in VHDL that can generate the start condition, send a 7-bit address with a write bit, and generate the stop condition on the I2C bus.

📋 What You'll Learn

Create signals for SDA and SCL lines

Create a signal for the 7-bit I2C address

Generate the I2C start condition

Send the 7-bit address with the write bit

Generate the I2C stop condition

💡 Why This Matters

🌍 Real World

I2C is a common communication protocol used in embedded systems to connect microcontrollers with sensors, memory chips, and other peripherals.

💼 Career

Understanding how to implement and control I2C communication in hardware description languages like VHDL is valuable for FPGA and ASIC design engineers working on embedded hardware.

1

Setup I2C signals and address

Create signals called SDA and SCL of type std_logic. Also create a 7-bit std_logic_vector signal called address and set it to "1010000".

VHDL

-- Your code here

Hint

Use signal keyword to declare signals. SDA and SCL are single bits, so use std_logic. The address is 7 bits, so use std_logic_vector(6 downto 0).

2

Create a start condition signal

Create a signal called start_condition of type std_logic and set it to '0'. This signal will represent the I2C start condition trigger.

VHDL

signal SDA : std_logic := '1';
signal SCL : std_logic := '1';
signal address : std_logic_vector(6 downto 0) := "1010000";
-- Your code here

Hint

Use signal start_condition : std_logic := '0'; to declare the start condition signal.

3

Generate start condition and send address

Write a process called I2C_Process triggered on the rising edge of a clock signal called clk. Inside, when start_condition = '1', set SDA low while SCL is high to generate the start condition. Then send the 7-bit address followed by a write bit '0' on SDA one bit at a time on falling edges of SCL. Use a variable bit_index to track bits sent from 6 down to 0.

VHDL

signal SDA : std_logic := '1';
signal SCL : std_logic := '1';
signal address : std_logic_vector(6 downto 0) := "1010000";
signal start_condition : std_logic := '0';
signal clk : std_logic := '0';
-- Your code here

Hint

Use a process triggered on clk. Inside, check start_condition. Generate start by setting SDA low when SCL is high. Then send bits on falling edge of SCL using bit_index.

4

Generate stop condition and display SDA, SCL

After sending the address and write bit, generate the stop condition by setting SDA high while SCL is high. Then write two lines to output the final values of SDA and SCL using report statements.

VHDL

signal SDA : std_logic := '1';
signal SCL : std_logic := '1';
signal address : std_logic_vector(6 downto 0) := "1010000";
signal start_condition : std_logic := '0';
signal clk : std_logic := '0';

process(clk)
    variable bit_index : integer := 6;
begin
    if rising_edge(clk) then
        if start_condition = '1' then
            if SCL = '1' then
                SDA = 0 then
                    SDA <= address(bit_index); -- Send address bits
                    bit_index := bit_index - 1;
                else
                    SDA <= '0'; -- Write bit
                end if;
            end if;
        end if;
    end if;
end process;

-- Your code here

Hint

After sending all bits, set SDA high while SCL is high to generate the stop condition. Use report to display SDA and SCL values.

Practice

1. What are the two main signals controlled by an I2C controller in VHDL?

easy

A. CLK and RESET

B. TX and RX

C. MOSI and MISO

D. SCL (clock) and SDA (data)

Solution

1. Step 1: Understand I2C communication basics

   I2C uses two wires: one for clock (SCL) and one for data (SDA).

2. Step 2: Identify signals controlled by the controller

   The I2C controller manages these two lines to send and receive data.

3. Final Answer:

   SCL (clock) and SDA (data) -> Option D

4. Quick Check:

   I2C signals = SCL and SDA [OK]

Hint: Remember: I2C always uses clock and data lines [OK]

Common Mistakes:

• Confusing I2C signals with SPI signals
• Thinking TX/RX are used in I2C
• Mixing up clock and reset signals

2. Which VHDL statement correctly declares the SDA line as an output signal in an I2C controller?

easy

A. signal SDA : out std_logic;

B. signal SDA : in std_logic;

C. signal SDA : buffer std_logic;

D. signal SDA : inout std_logic;

Solution

1. Step 1: Recall VHDL signal directions

   Output signals are declared with the keyword 'out'.

2. Step 2: Match SDA line direction

   SDA is controlled by the I2C controller to send data, so it must be 'out'.

3. Final Answer:

   signal SDA : out std_logic; -> Option A

4. Quick Check:

   Output signal = 'out' [OK]

Hint: Output signals use 'out' keyword in VHDL [OK]

Common Mistakes:

• Using 'in' instead of 'out' for output signals
• Confusing 'buffer' and 'out' keywords
• Using 'inout' when only output is needed

3. Given this VHDL snippet for generating a start condition in I2C, what is the value of SDA after execution?

process(clk)
begin
  if rising_edge(clk) then
    SDA <= '1';
    SCL <= '1';
    SDA <= '0'; -- start condition
  end if;
end process;

medium

A. '1'

B. '0'

C. Undefined (multiple assignments in one clock)

D. Remains previous value

Solution

1. Step 1: Analyze signal assignments in process

   Within the same clock edge, SDA is first set to '1', then immediately to '0'.

2. Step 2: Understand signal assignment behavior in VHDL

   Last assignment in the process overrides previous ones, so SDA becomes '0'.

3. Final Answer:

   '0' -> Option B

4. Quick Check:

   Last assignment wins = '0' [OK]

Hint: Last signal assignment in process sets final value [OK]

Common Mistakes:

• Assuming first assignment sticks
• Thinking multiple assignments cause error
• Ignoring VHDL signal update rules

4. Identify the error in this VHDL code snippet for generating a stop condition in I2C:

process(clk)
begin
  if rising_edge(clk) then
    SDA <= '0';
    SCL <= '1';
    SDA <= '1'; -- stop condition
  end if;
end process;

medium

A. SDA should be set to '1' before SCL is '1'

B. No error, code is correct

C. Multiple assignments to SDA in one clock cause conflict

D. Stop condition requires SDA to go low, not high

Solution

1. Step 1: Review SDA assignments in the process

   SDA is assigned '0' then '1' in the same clock cycle.

2. Step 2: Understand VHDL signal assignment rules

   Multiple assignments to the same signal in one clock can cause unexpected behavior or synthesis issues.

3. Final Answer:

   Multiple assignments to SDA in one clock cause conflict -> Option C

4. Quick Check:

   Multiple assignments = conflict [OK]

Hint: Avoid multiple assignments to same signal in one clock [OK]

Common Mistakes:

• Ignoring multiple assignments problem
• Confusing start and stop condition logic
• Assuming code runs without synthesis warnings

5. You want to design an I2C controller in VHDL that sends a start condition, then transmits 8 bits of data, and finally sends a stop condition. Which sequence of signal changes correctly represents this process?

hard

A. SDA goes from high to low while SCL is high (start), then data bits sent on SDA with SCL toggling, then SDA goes low to high while SCL is high (stop)

B. SDA goes low to high while SCL is low (start), then data bits sent on SDA with SCL low, then SDA goes high to low while SCL is low (stop)

C. SCL stays low throughout, SDA toggles for start, data, and stop

D. SDA and SCL both toggle randomly during start, data, and stop

Solution

1. Step 1: Recall I2C start and stop conditions

   Start condition: SDA falls from high to low while SCL is high. Stop condition: SDA rises from low to high while SCL is high.

2. Step 2: Understand data transmission timing

   Data bits are sent on SDA line while toggling SCL clock line to synchronize bits.

3. Step 3: Match sequence to options

   SDA goes from high to low while SCL is high (start), then data bits sent on SDA with SCL toggling, then SDA goes low to high while SCL is high (stop) correctly describes the start, data, and stop signal changes.

4. Final Answer:

   Start: SDA high to low while SCL high, data sent with SCL toggling, stop: SDA low to high while SCL high -> Option A

5. Quick Check:

   Start/stop conditions require SDA change while SCL high [OK]

Hint: Start/stop change SDA only when SCL is high [OK]

Common Mistakes:

• Changing SDA when SCL is low for start/stop
• Not toggling SCL during data bits
• Confusing start and stop signal directions