Three-process FSM coding style in VHDL - Step-by-Step Execution

Concept Flow - Three-process FSM coding style

Input Signals

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Process 1: State Register

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Process 2: Next State Logic

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Process 3: Output Logic

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Outputs Updated

↩Back to Input Signals

The FSM uses three processes: one to store the current state, one to decide the next state, and one to set outputs based on the current state.

Execution Sample

VHDL

process(clk, reset)
begin
  if reset = '1' then
    state <= IDLE;
  elsif rising_edge(clk) then
    state <= next_state;
  end if;
end process;

This process updates the current state on clock edge or resets it.

Execution Table

Step	clk	reset	state (before)	next_state	state (after)	Output
1	0	1	IDLE	IDLE	IDLE	output_idle
2	1 (rising)	0	IDLE	WORK	WORK	output_work
3	0	0	WORK	WORK	WORK	output_work
4	1 (rising)	0	WORK	DONE	DONE	output_done
5	1 (rising)	1	DONE	IDLE	IDLE	output_idle
6	1 (rising)	0	IDLE	IDLE	IDLE	output_idle

💡 Simulation stops after reset returns to '0' and state cycles through IDLE, WORK, DONE.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	Final
clk	0	1	0	1	1	1	1
reset	1	0	0	0	1	0	0
state	IDLE	IDLE	WORK	WORK	DONE	IDLE	IDLE
next_state	IDLE	WORK	WORK	DONE	IDLE	IDLE	IDLE
Output	output_idle	output_work	output_work	output_done	output_idle	output_idle	output_idle

Key Moments - 3 Insights

Why does the state not change immediately when next_state changes?

Because the state updates only on the rising edge of clk as shown in execution_table rows 2 and 4, the next_state is computed combinationally but state changes synchronously.

What happens when reset is '1' during a clock edge?

The state is forced to IDLE immediately regardless of next_state, as shown in row 5 where reset=1 causes state to reset.

Why do we separate next state logic and output logic into different processes?

Separating them keeps the design clear: next state logic decides transitions, output logic sets outputs based on current state, avoiding combinational loops and making debugging easier.

Visual Quiz - 3 Questions

Look at the execution table, what is the state after step 3?

A WORK

B IDLE

C DONE

D RESET

💡 Hint

Check the 'state (after)' column at step 3 in the execution_table.

At which step does reset cause the state to return to IDLE?

A Step 2

B Step 5

C Step 4

D Step 6

💡 Hint

Look for reset='1' in the execution_table and see which step resets the state.

If clk did not have a rising edge at step 2, what would state be after step 2?

A WORK

B DONE

C IDLE

D Undefined

💡 Hint

State updates only on rising edge of clk, see execution_table step 2 condition.

Concept Snapshot

Three-process FSM style in VHDL:
1) State register process: updates state on clock edge or reset.
2) Next state logic process: combinational logic to decide next state.
3) Output logic process: combinational logic for outputs based on current state.
This separation improves clarity and avoids timing issues.

Full Transcript

This visual execution shows a three-process FSM in VHDL. The first process updates the current state on the rising clock edge or resets it. The second process calculates the next state based on inputs and current state. The third process sets outputs depending on the current state. The execution table traces clock, reset, state before and after, next state, and output values step-by-step. Key moments clarify why state changes only on clock edges and how reset forces state to IDLE. The quiz tests understanding of state changes and reset effects. This style keeps FSM design clean and easy to follow.

Practice

1. In the three-process FSM coding style in VHDL, which process is responsible for storing the current state?

easy

A. The next state logic process

B. The state register process

C. The output logic process

D. The clock generation process

Solution

1. Step 1: Understand the role of each process

   The three-process FSM style divides the FSM into state register, next state logic, and output logic processes.

2. Step 2: Identify which process stores the current state

   The state register process updates and stores the current state on clock edges.

3. Final Answer:

   The state register process -> Option B

4. Quick Check:

   State storage = state register process [OK]

Hint: State storage always happens in the state register process [OK]

Common Mistakes:

• Confusing next state logic with state storage
• Thinking output logic stores the state
• Assuming clock generation is part of FSM

2. Which of the following is the correct sensitivity list for the next state logic process in a three-process FSM?

easy

A. clk, reset

B. clk

C. outputs

D. current_state, inputs

Solution

1. Step 1: Recall what next state logic depends on

   The next state logic calculates the next state based on the current state and inputs.

2. Step 2: Determine the sensitivity list

   It must react to changes in current_state and inputs, so these go in the sensitivity list.

3. Final Answer:

   current_state, inputs -> Option D

4. Quick Check:

   Next state logic sensitivity = current_state, inputs [OK]

Hint: Next state logic sensitive to current state and inputs only [OK]

Common Mistakes:

• Including clk in next state logic sensitivity list
• Using outputs in sensitivity list
• Leaving sensitivity list empty

3. Given the following partial FSM code snippet, what will be the output value of output_signal when current_state is S1 and input_signal is '1'?

process(current_state, input_signal)
begin
  case current_state is
    when S0 => output_signal <= '0';
    when S1 =>
      if input_signal = '1' then
        output_signal <= '1';
      else
        output_signal <= '0';
      end if;
    when others => output_signal <= '0';
  end case;
end process;

medium

A. Undefined

B. '0'

C. '1'

D. Signal retains previous value

Solution

1. Step 1: Analyze the output logic for state S1

   When current_state is S1, output_signal is '1' if input_signal is '1', else '0'.

2. Step 2: Apply given inputs

   current_state = S1 and input_signal = '1' means output_signal <= '1'.

3. Final Answer:

   '1' -> Option C

4. Quick Check:

   Output for S1 with input '1' = '1' [OK]

Hint: Check state and input conditions carefully for output logic [OK]

Common Mistakes:

• Ignoring input condition inside S1
• Assuming output is always '0' in S1
• Confusing output logic with next state logic

4. Identify the error in this state register process code snippet for a three-process FSM:

process(clk, reset)
begin
  if reset = '1' then
    current_state <= S0;
  elsif rising_edge(clk) then
    next_state <= current_state;
  end if;
end process;

medium

A. Using next_state instead of current_state on clock edge

B. Missing sensitivity to next_state signal

C. Reset condition should be inside rising_edge(clk)

D. No error, code is correct

Solution

1. Step 1: Understand state register role

   The state register updates current_state with next_state on clock edge.

2. Step 2: Check assignment inside clock edge

   The code assigns next_state <= current_state, which is reversed and wrong.

3. Final Answer:

   Using next_state instead of current_state on clock edge -> Option A

4. Quick Check:

   State register updates current_state, not next_state [OK]

Hint: State register updates current_state from next_state [OK]

Common Mistakes:

• Assigning next_state inside state register process
• Placing reset inside clock edge condition
• Confusing current_state and next_state signals

5. You want to design a three-process FSM with states IDLE, BUSY, and DONE. Which of the following correctly describes the responsibilities of the three processes?

hard

A. Process 1: Store current state; Process 2: Compute next state from current state and inputs; Process 3: Generate outputs based on current state

B. Process 1: Generate outputs; Process 2: Store current state; Process 3: Compute next state

C. Process 1: Compute next state; Process 2: Generate outputs; Process 3: Store current state

D. Process 1: Store current state and outputs; Process 2: Compute next state; Process 3: Reset FSM

Solution

1. Step 1: Recall three-process FSM roles

   The three processes are: state register (store current state), next state logic (compute next state), output logic (generate outputs).

2. Step 2: Match roles to options

   Process 1: Store current state; Process 2: Compute next state from current state and inputs; Process 3: Generate outputs based on current state correctly assigns these roles in order.

3. Final Answer:

   Process 1: Store current state; Process 2: Compute next state from current state and inputs; Process 3: Generate outputs based on current state -> Option A

4. Quick Check:

   Three-process FSM roles = B [OK]

Hint: Remember: register stores state, logic computes next, output drives signals [OK]

Common Mistakes:

• Mixing output generation with state storage
• Assigning reset to a separate process
• Combining multiple roles in one process