Three-process FSM coding style in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the state type in a three-process FSM.

VHDL

type state_type is (IDLE, PROCESS, DONE);
signal current_state : state_type := [1];

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ADONE

BPROCESS

CIDLE

DSTART

Attempts:

3 left

💡 Hint

Common Mistakes

Choosing a state that is not defined in the type.

Using a string instead of the state name.

The initial state is usually set to IDLE to start the FSM in a known state.

2fill in blank

medium

Complete the code to write the synchronous process for state transitions.

VHDL

process(clk, reset)
begin
  if reset = '1' then
    current_state <= IDLE;
  elsif rising_edge(clk) then
    current_state <= [1];
  end if;
end process;

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Acurrent_state

Bnext_state

Cstate

Dprev_state

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning current_state to itself causing no state change.

Using an undefined signal name.

The synchronous process updates current_state to the value of next_state on the clock edge.

3fill in blank

hard

Fix the error in the combinational process for next state logic.

VHDL

process(current_state, start, done)
begin
  case current_state is
    when IDLE =>
      if start = '1' then
        next_state <= [1];
      else
        next_state <= IDLE;
      end if;
    when PROCESS =>
      if done = '1' then
        next_state <= DONE;
      else
        next_state <= PROCESS;
      end if;
    when DONE =>
      next_state <= IDLE;
    when others =>
      next_state <= IDLE;
  end case;
end process;

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APROCESS

BSTART

CIDLE

DDONE

Attempts:

3 left

💡 Hint

Common Mistakes

Setting next_state to DONE directly from IDLE.

Using an undefined state like START.

When in IDLE and start = '1', the FSM should move to the PROCESS state.

4fill in blank

hard

Fill both blanks to complete the output logic process.

VHDL

process(current_state)
begin
  case current_state is
    when IDLE => output_signal <= [1];
    when PROCESS => output_signal <= [2];
    when DONE => output_signal <= '1';
    when others => output_signal <= '0';
  end case;
end process;

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A'0'

B'1'

C'Z'

D'X'

Attempts:

3 left

💡 Hint

Common Mistakes

Using high impedance ('Z') for output signal.

Assigning output '1' in IDLE state.

Output is '0' in IDLE and '1' in PROCESS state to indicate activity.

5fill in blank

hard

Fill all three blanks to complete the reset and clock sensitivity list in the synchronous process.

VHDL

process([1], [2])
begin
  if [3] = '1' then
    current_state <= IDLE;
  elsif rising_edge(clk) then
    current_state <= next_state;
  end if;
end process;

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Areset

Bclk

Creset_n

Denable

Attempts:

3 left

💡 Hint

Common Mistakes

Using an incorrect signal like enable in sensitivity list.

Checking reset_n instead of reset when reset is active high.

The process is sensitive to reset and clk. The reset signal is checked for '1' to initialize the FSM.

Practice

1. In the three-process FSM coding style in VHDL, which process is responsible for storing the current state?

easy

A. The next state logic process

B. The state register process

C. The output logic process

D. The clock generation process

Solution

1. Step 1: Understand the role of each process

   The three-process FSM style divides the FSM into state register, next state logic, and output logic processes.

2. Step 2: Identify which process stores the current state

   The state register process updates and stores the current state on clock edges.

3. Final Answer:

   The state register process -> Option B

4. Quick Check:

   State storage = state register process [OK]

Hint: State storage always happens in the state register process [OK]

Common Mistakes:

• Confusing next state logic with state storage
• Thinking output logic stores the state
• Assuming clock generation is part of FSM

2. Which of the following is the correct sensitivity list for the next state logic process in a three-process FSM?

easy

A. clk, reset

B. clk

C. outputs

D. current_state, inputs

Solution

1. Step 1: Recall what next state logic depends on

   The next state logic calculates the next state based on the current state and inputs.

2. Step 2: Determine the sensitivity list

   It must react to changes in current_state and inputs, so these go in the sensitivity list.

3. Final Answer:

   current_state, inputs -> Option D

4. Quick Check:

   Next state logic sensitivity = current_state, inputs [OK]

Hint: Next state logic sensitive to current state and inputs only [OK]

Common Mistakes:

• Including clk in next state logic sensitivity list
• Using outputs in sensitivity list
• Leaving sensitivity list empty

3. Given the following partial FSM code snippet, what will be the output value of output_signal when current_state is S1 and input_signal is '1'?

process(current_state, input_signal)
begin
  case current_state is
    when S0 => output_signal <= '0';
    when S1 =>
      if input_signal = '1' then
        output_signal <= '1';
      else
        output_signal <= '0';
      end if;
    when others => output_signal <= '0';
  end case;
end process;

medium

A. Undefined

B. '0'

C. '1'

D. Signal retains previous value

Solution

1. Step 1: Analyze the output logic for state S1

   When current_state is S1, output_signal is '1' if input_signal is '1', else '0'.

2. Step 2: Apply given inputs

   current_state = S1 and input_signal = '1' means output_signal <= '1'.

3. Final Answer:

   '1' -> Option C

4. Quick Check:

   Output for S1 with input '1' = '1' [OK]

Hint: Check state and input conditions carefully for output logic [OK]

Common Mistakes:

• Ignoring input condition inside S1
• Assuming output is always '0' in S1
• Confusing output logic with next state logic

4. Identify the error in this state register process code snippet for a three-process FSM:

process(clk, reset)
begin
  if reset = '1' then
    current_state <= S0;
  elsif rising_edge(clk) then
    next_state <= current_state;
  end if;
end process;

medium

A. Using next_state instead of current_state on clock edge

B. Missing sensitivity to next_state signal

C. Reset condition should be inside rising_edge(clk)

D. No error, code is correct

Solution

1. Step 1: Understand state register role

   The state register updates current_state with next_state on clock edge.

2. Step 2: Check assignment inside clock edge

   The code assigns next_state <= current_state, which is reversed and wrong.

3. Final Answer:

   Using next_state instead of current_state on clock edge -> Option A

4. Quick Check:

   State register updates current_state, not next_state [OK]

Hint: State register updates current_state from next_state [OK]

Common Mistakes:

• Assigning next_state inside state register process
• Placing reset inside clock edge condition
• Confusing current_state and next_state signals

5. You want to design a three-process FSM with states IDLE, BUSY, and DONE. Which of the following correctly describes the responsibilities of the three processes?

hard

A. Process 1: Store current state; Process 2: Compute next state from current state and inputs; Process 3: Generate outputs based on current state

B. Process 1: Generate outputs; Process 2: Store current state; Process 3: Compute next state

C. Process 1: Compute next state; Process 2: Generate outputs; Process 3: Store current state

D. Process 1: Store current state and outputs; Process 2: Compute next state; Process 3: Reset FSM

Solution

1. Step 1: Recall three-process FSM roles

   The three processes are: state register (store current state), next state logic (compute next state), output logic (generate outputs).

2. Step 2: Match roles to options

   Process 1: Store current state; Process 2: Compute next state from current state and inputs; Process 3: Generate outputs based on current state correctly assigns these roles in order.

3. Final Answer:

   Process 1: Store current state; Process 2: Compute next state from current state and inputs; Process 3: Generate outputs based on current state -> Option A

4. Quick Check:

   Three-process FSM roles = B [OK]

Hint: Remember: register stores state, logic computes next, output drives signals [OK]

Common Mistakes:

• Mixing output generation with state storage
• Assigning reset to a separate process
• Combining multiple roles in one process