Three-process FSM coding style in VHDL - Cheat Sheet & Quick Revision

Recall & Review

beginner

What are the three main processes in a three-process FSM coding style in VHDL?

The three main processes are:
1. State register process (handles state updates)
2. Next-state logic process (determines the next state)
3. Output logic process (generates outputs based on the current state)

intermediate

Why is the three-process FSM style preferred over a single-process FSM in VHDL?

Because it separates state storage, next-state logic, and output logic clearly, making the design easier to read, debug, and maintain. It also helps avoid unintended latches and improves synthesis results.

beginner

In the state register process of a three-process FSM, what triggers the state update?

The state update is triggered by the rising edge of the clock and optionally by an asynchronous reset signal to initialize the state.

beginner

What is the role of the next-state logic process in a three-process FSM?

It computes the next state based on the current state and inputs, without changing the current state directly.

intermediate

How does the output logic process in a three-process FSM differ from Moore and Mealy outputs?

The output logic process can implement Moore outputs (dependent only on the current state) or Mealy outputs (dependent on state and inputs), depending on design needs, but it is kept separate from state and next-state logic.

Which process in a three-process FSM updates the current state?

A State register process

B Next-state logic process

C Output logic process

D Input sampling process

The state register process updates the current state on the clock edge.

What does the next-state logic process use to decide the next state?

A Outputs

B Only inputs

C Current state and inputs

D Only current state

The next-state logic process uses both the current state and inputs to determine the next state.

In a three-process FSM, where should output signals be assigned?

A In the state register process

B In the clock process

C In the next-state logic process

D In the output logic process

Outputs are assigned in the output logic process to keep logic clear and separated.

What is a key advantage of separating FSM logic into three processes?

A Reduces the number of signals

B Improves readability and debugging

C Eliminates the need for a clock

D Makes the FSM asynchronous

Separating FSM logic improves readability and makes debugging easier.

Which of these is NOT typically part of the three-process FSM style?

A Input debounce process

B Next-state logic process

C State register process

D Output logic process

Input debounce is unrelated to the FSM three-process style.

Describe the purpose of each of the three processes in a three-process FSM coding style.

Think about how the FSM stores state, decides next state, and produces outputs.

Explain why separating FSM logic into three processes can help avoid unintended latches.

Consider how combinational logic and clocked logic differ.

Practice

1. In the three-process FSM coding style in VHDL, which process is responsible for storing the current state?

easy

A. The next state logic process

B. The state register process

C. The output logic process

D. The clock generation process

Solution

1. Step 1: Understand the role of each process

   The three-process FSM style divides the FSM into state register, next state logic, and output logic processes.

2. Step 2: Identify which process stores the current state

   The state register process updates and stores the current state on clock edges.

3. Final Answer:

   The state register process -> Option B

4. Quick Check:

   State storage = state register process [OK]

Hint: State storage always happens in the state register process [OK]

Common Mistakes:

• Confusing next state logic with state storage
• Thinking output logic stores the state
• Assuming clock generation is part of FSM

2. Which of the following is the correct sensitivity list for the next state logic process in a three-process FSM?

easy

A. clk, reset

B. clk

C. outputs

D. current_state, inputs

Solution

1. Step 1: Recall what next state logic depends on

   The next state logic calculates the next state based on the current state and inputs.

2. Step 2: Determine the sensitivity list

   It must react to changes in current_state and inputs, so these go in the sensitivity list.

3. Final Answer:

   current_state, inputs -> Option D

4. Quick Check:

   Next state logic sensitivity = current_state, inputs [OK]

Hint: Next state logic sensitive to current state and inputs only [OK]

Common Mistakes:

• Including clk in next state logic sensitivity list
• Using outputs in sensitivity list
• Leaving sensitivity list empty

3. Given the following partial FSM code snippet, what will be the output value of output_signal when current_state is S1 and input_signal is '1'?

process(current_state, input_signal)
begin
  case current_state is
    when S0 => output_signal <= '0';
    when S1 =>
      if input_signal = '1' then
        output_signal <= '1';
      else
        output_signal <= '0';
      end if;
    when others => output_signal <= '0';
  end case;
end process;

medium

A. Undefined

B. '0'

C. '1'

D. Signal retains previous value

Solution

1. Step 1: Analyze the output logic for state S1

   When current_state is S1, output_signal is '1' if input_signal is '1', else '0'.

2. Step 2: Apply given inputs

   current_state = S1 and input_signal = '1' means output_signal <= '1'.

3. Final Answer:

   '1' -> Option C

4. Quick Check:

   Output for S1 with input '1' = '1' [OK]

Hint: Check state and input conditions carefully for output logic [OK]

Common Mistakes:

• Ignoring input condition inside S1
• Assuming output is always '0' in S1
• Confusing output logic with next state logic

4. Identify the error in this state register process code snippet for a three-process FSM:

process(clk, reset)
begin
  if reset = '1' then
    current_state <= S0;
  elsif rising_edge(clk) then
    next_state <= current_state;
  end if;
end process;

medium

A. Using next_state instead of current_state on clock edge

B. Missing sensitivity to next_state signal

C. Reset condition should be inside rising_edge(clk)

D. No error, code is correct

Solution

1. Step 1: Understand state register role

   The state register updates current_state with next_state on clock edge.

2. Step 2: Check assignment inside clock edge

   The code assigns next_state <= current_state, which is reversed and wrong.

3. Final Answer:

   Using next_state instead of current_state on clock edge -> Option A

4. Quick Check:

   State register updates current_state, not next_state [OK]

Hint: State register updates current_state from next_state [OK]

Common Mistakes:

• Assigning next_state inside state register process
• Placing reset inside clock edge condition
• Confusing current_state and next_state signals

5. You want to design a three-process FSM with states IDLE, BUSY, and DONE. Which of the following correctly describes the responsibilities of the three processes?

hard

A. Process 1: Store current state; Process 2: Compute next state from current state and inputs; Process 3: Generate outputs based on current state

B. Process 1: Generate outputs; Process 2: Store current state; Process 3: Compute next state

C. Process 1: Compute next state; Process 2: Generate outputs; Process 3: Store current state

D. Process 1: Store current state and outputs; Process 2: Compute next state; Process 3: Reset FSM

Solution

1. Step 1: Recall three-process FSM roles

   The three processes are: state register (store current state), next state logic (compute next state), output logic (generate outputs).

2. Step 2: Match roles to options

   Process 1: Store current state; Process 2: Compute next state from current state and inputs; Process 3: Generate outputs based on current state correctly assigns these roles in order.

3. Final Answer:

   Process 1: Store current state; Process 2: Compute next state from current state and inputs; Process 3: Generate outputs based on current state -> Option A

4. Quick Check:

   Three-process FSM roles = B [OK]

Hint: Remember: register stores state, logic computes next, output drives signals [OK]

Common Mistakes:

• Mixing output generation with state storage
• Assigning reset to a separate process
• Combining multiple roles in one process