Three-process FSM coding style in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a three-process FSM with synchronous reset

Consider this VHDL snippet of a three-process FSM with synchronous reset. What will be the value of state after the first rising clock edge when reset is '1'?

VHDL

architecture Behavioral of fsm is
  type state_type is (IDLE, WORK, DONE);
  signal state, next_state: state_type := IDLE;
begin
  -- State register process
  process(clk)
  begin
    if rising_edge(clk) then
      if reset = '1' then
        state <= IDLE;
      else
        state <= next_state;
      end if;
    end if;
  end process;

  -- Next state logic process
  process(state, start)
  begin
    case state is
      when IDLE =>
        if start = '1' then
          next_state <= WORK;
        else
          next_state <= IDLE;
        end if;
      when WORK =>
        next_state <= DONE;
      when DONE =>
        next_state <= IDLE;
    end case;
  end process;

  -- Output logic process
  process(state)
  begin
    done <= '0';
    case state is
      when DONE =>
        done <= '1';
      when others =>
        done <= '0';
    end case;
  end process;
end Behavioral;

A state = IDLE

B state = WORK

C state = DONE

D state is undefined

💡 Hint

Remember that synchronous reset sets the state at the clock edge.

Since reset is '1' at the rising edge, the state register process sets state to IDLE. The next state logic does not affect the current state immediately.

❓ Predict Output

intermediate

Next state after start signal in three-process FSM

Given the same FSM as above, if reset is '0' and start is '1' at the rising clock edge, what will be the value of next_state immediately after the clock edge?

VHDL

Same as challenge c1

A next_state is undefined

B next_state = IDLE

C next_state = DONE

D next_state = WORK

💡 Hint

Check the next state logic process for the IDLE state when start is '1'.

When in IDLE and start is '1', the next state logic sets next_state to WORK.

🔧 Debug

advanced

Identify the error in the state register process

Which option contains an error that will cause the state register process to not work as intended in a three-process FSM?

VHDL

process(clk)
begin
  if rising_edge(clk) then
    if reset = '1' then
      state <= IDLE;
    else
      state <= next_state;
    end if;
  end if;
end process;

A

process(clk)
begin
  if rising_edge(clk) then
    if reset = '1' then
      next_state <= IDLE;
    else
      state <= next_state;
    end if;
  end if;
end process;

B

process(clk)
begin
  if clk'event and clk = '1' then
    if reset = '1' then
      state <= IDLE;
    else
      state <= next_state;
    end if;
  end if;
end process;

C

process(clk)
begin
  if rising_edge(clk) then
    if reset = '1' then
      state <= IDLE;
    else
      state <= next_state;
    end if;
  end if;
end process;

D

process(clk)
begin
  if rising_edge(clk) then
    if reset = '1' then
      state <= IDLE;
    else
      state <= state;
    end if;
  end if;
end process;

💡 Hint

Check which signal is assigned inside the state register process.

Option A incorrectly assigns next_state inside the state register process instead of state. This breaks the FSM behavior.

📝 Syntax

advanced

Syntax error in output logic process

Which option contains a syntax error in the output logic process of a three-process FSM?

VHDL

process(state)
begin
  done <= '0';
  case state is
    when DONE =>
      done <= '1';
    when others =>
      done <= '0';
  end case;
end process;

A

;ssecorp dne
;esac dne  
;'0' =< enod      
>= srehto nehw    
;'1' =< enod      
>= ENOD nehw    
si etats esac  
;'0' =< enod  
nigeb
)etats(ssecorp

B

process(state)
begin
  done <= '0';
  case state is
    when DONE =>
      done <= '1';
    when others =>
      done <= '0';
  end case;
end process;

C

process(state)
begin
  done <= '0';
  case state is
    when DONE =>
      done <= '1';
    when others =>
      done <= '0';
  end case
end process;

D

rocess(state)
begin
  done <= '0';
  case state is
    when DONE =>
      done <= '1';
    when others =>
      done <= '0';
  end case;
end process;

💡 Hint

Check for missing semicolons and correct case syntax.

Option C is missing the semicolon after end case, causing a syntax error.

🚀 Application

expert

Number of states and outputs in a three-process FSM

A three-process FSM has the states IDLE, WORK, and DONE. The output done is '1' only in the DONE state. How many unique output values and states does this FSM have?

A 2 states, 1 unique output value

B 3 states, 2 unique output values

C 2 states, 2 unique output values

D 3 states, 3 unique output values

💡 Hint

Count the states and distinct output values based on the output logic.

The FSM has three states: IDLE, WORK, and DONE. The output done is '1' only in DONE, and '0' otherwise, so there are two unique output values.

Practice

1. In the three-process FSM coding style in VHDL, which process is responsible for storing the current state?

easy

A. The next state logic process

B. The state register process

C. The output logic process

D. The clock generation process

Solution

1. Step 1: Understand the role of each process

   The three-process FSM style divides the FSM into state register, next state logic, and output logic processes.

2. Step 2: Identify which process stores the current state

   The state register process updates and stores the current state on clock edges.

3. Final Answer:

   The state register process -> Option B

4. Quick Check:

   State storage = state register process [OK]

Hint: State storage always happens in the state register process [OK]

Common Mistakes:

• Confusing next state logic with state storage
• Thinking output logic stores the state
• Assuming clock generation is part of FSM

2. Which of the following is the correct sensitivity list for the next state logic process in a three-process FSM?

easy

A. clk, reset

B. clk

C. outputs

D. current_state, inputs

Solution

1. Step 1: Recall what next state logic depends on

   The next state logic calculates the next state based on the current state and inputs.

2. Step 2: Determine the sensitivity list

   It must react to changes in current_state and inputs, so these go in the sensitivity list.

3. Final Answer:

   current_state, inputs -> Option D

4. Quick Check:

   Next state logic sensitivity = current_state, inputs [OK]

Hint: Next state logic sensitive to current state and inputs only [OK]

Common Mistakes:

• Including clk in next state logic sensitivity list
• Using outputs in sensitivity list
• Leaving sensitivity list empty

3. Given the following partial FSM code snippet, what will be the output value of output_signal when current_state is S1 and input_signal is '1'?

process(current_state, input_signal)
begin
  case current_state is
    when S0 => output_signal <= '0';
    when S1 =>
      if input_signal = '1' then
        output_signal <= '1';
      else
        output_signal <= '0';
      end if;
    when others => output_signal <= '0';
  end case;
end process;

medium

A. Undefined

B. '0'

C. '1'

D. Signal retains previous value

Solution

1. Step 1: Analyze the output logic for state S1

   When current_state is S1, output_signal is '1' if input_signal is '1', else '0'.

2. Step 2: Apply given inputs

   current_state = S1 and input_signal = '1' means output_signal <= '1'.

3. Final Answer:

   '1' -> Option C

4. Quick Check:

   Output for S1 with input '1' = '1' [OK]

Hint: Check state and input conditions carefully for output logic [OK]

Common Mistakes:

• Ignoring input condition inside S1
• Assuming output is always '0' in S1
• Confusing output logic with next state logic

4. Identify the error in this state register process code snippet for a three-process FSM:

process(clk, reset)
begin
  if reset = '1' then
    current_state <= S0;
  elsif rising_edge(clk) then
    next_state <= current_state;
  end if;
end process;

medium

A. Using next_state instead of current_state on clock edge

B. Missing sensitivity to next_state signal

C. Reset condition should be inside rising_edge(clk)

D. No error, code is correct

Solution

1. Step 1: Understand state register role

   The state register updates current_state with next_state on clock edge.

2. Step 2: Check assignment inside clock edge

   The code assigns next_state <= current_state, which is reversed and wrong.

3. Final Answer:

   Using next_state instead of current_state on clock edge -> Option A

4. Quick Check:

   State register updates current_state, not next_state [OK]

Hint: State register updates current_state from next_state [OK]

Common Mistakes:

• Assigning next_state inside state register process
• Placing reset inside clock edge condition
• Confusing current_state and next_state signals

5. You want to design a three-process FSM with states IDLE, BUSY, and DONE. Which of the following correctly describes the responsibilities of the three processes?

hard

A. Process 1: Store current state; Process 2: Compute next state from current state and inputs; Process 3: Generate outputs based on current state

B. Process 1: Generate outputs; Process 2: Store current state; Process 3: Compute next state

C. Process 1: Compute next state; Process 2: Generate outputs; Process 3: Store current state

D. Process 1: Store current state and outputs; Process 2: Compute next state; Process 3: Reset FSM

Solution

1. Step 1: Recall three-process FSM roles

   The three processes are: state register (store current state), next state logic (compute next state), output logic (generate outputs).

2. Step 2: Match roles to options

   Process 1: Store current state; Process 2: Compute next state from current state and inputs; Process 3: Generate outputs based on current state correctly assigns these roles in order.

3. Final Answer:

   Process 1: Store current state; Process 2: Compute next state from current state and inputs; Process 3: Generate outputs based on current state -> Option A

4. Quick Check:

   Three-process FSM roles = B [OK]

Hint: Remember: register stores state, logic computes next, output drives signals [OK]

Common Mistakes:

• Mixing output generation with state storage
• Assigning reset to a separate process
• Combining multiple roles in one process