Three-process FSM coding style in VHDL - Mini Project: Build & Apply

Three-process FSM coding style in VHDL

📖 Scenario: You are designing a simple traffic light controller using VHDL. The traffic light cycles through three states: Green, Yellow, and Red. You will implement this controller using the three-process FSM coding style, which separates state register, next state logic, and output logic into three distinct processes.

🎯 Goal: Build a three-process FSM in VHDL that controls a traffic light with states Green, Yellow, and Red. The FSM should cycle through these states in order, changing state on each clock cycle. Outputs should reflect the current state by turning on the corresponding light signal.

📋 What You'll Learn

Create a state type with states Green, Yellow, and Red

Create a signal current_state to hold the FSM state

Create a synchronous process to update current_state on the rising edge of clk and reset it to Green on reset

Create a combinational process to determine next_state based on current_state

Create a combinational process to set output signals green_light, yellow_light, and red_light based on current_state

Print the current state name as a string in simulation output

💡 Why This Matters

🌍 Real World

Traffic light controllers are common real-world examples of FSMs used in embedded systems and digital design.

💼 Career

Understanding three-process FSM coding style is essential for hardware engineers and FPGA developers to write clear, maintainable, and synthesizable VHDL code.

1

Define the FSM states and state signal

Define a VHDL type called state_type with states Green, Yellow, and Red. Then declare a signal called current_state of type state_type.

VHDL

-- Define the state_type and current_state signal
-- Your code here

Hint

Use type state_type is (Green, Yellow, Red); to define states and signal current_state : state_type; to declare the state signal.

2

Create the synchronous process for state register

Add a process sensitive to clk and reset that updates current_state on the rising edge of clk. On reset = '1', set current_state to Green.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity traffic_light is
    port(
        clk : in std_logic;
        reset : in std_logic;
        green_light : out std_logic;
        yellow_light : out std_logic;
        red_light : out std_logic
    );
end traffic_light;

architecture Behavioral of traffic_light is
    type state_type is (Green, Yellow, Red);
    signal current_state : state_type;
begin
    -- Add synchronous process to update current_state
    -- Your code here
end Behavioral;

Hint

Use a process with if reset = '1' to set current_state to Green. Use elsif rising_edge(clk) to update current_state.

3

Add combinational process for next state logic

Declare a signal next_state of type state_type. Add a combinational process that sets next_state based on current_state: Green goes to Yellow, Yellow goes to Red, and Red goes to Green. Update the synchronous process to assign current_state <= next_state on clock rising edge.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity traffic_light is
    port(
        clk : in std_logic;
        reset : in std_logic;
        green_light : out std_logic;
        yellow_light : out std_logic;
        red_light : out std_logic
    );
end traffic_light;

architecture Behavioral of traffic_light is
    type state_type is (Green, Yellow, Red);
    signal current_state : state_type;
    -- Declare next_state signal here
    -- Your code here
begin
    process(clk, reset)
    begin
        if reset = '1' then
            current_state <= Green;
        elsif rising_edge(clk) then
            -- Update current_state with next_state
            -- Your code here
        end if;
    end process;

    -- Add combinational process for next_state logic
    -- Your code here
end Behavioral;

Hint

Declare next_state signal. Use a process with case current_state is to set next_state. Update current_state <= next_state in the clocked process.

4

Add output logic and print current state

Add a combinational process that sets green_light, yellow_light, and red_light to '1' when current_state is Green, Yellow, or Red respectively, and '0' otherwise. Also, add a process that prints the current state name as a string to the simulation output on each clock rising edge.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.std_logic_textio.all;

entity traffic_light is
    port(
        clk : in std_logic;
        reset : in std_logic;
        green_light : out std_logic;
        yellow_light : out std_logic;
        red_light : out std_logic
    );
end traffic_light;

architecture Behavioral of traffic_light is
    type state_type is (Green, Yellow, Red);
    signal current_state : state_type;
    signal next_state : state_type;
    file output_file : text open write_mode is "output.log";
begin
    process(clk, reset)
    begin
        if reset = '1' then
            current_state 
                next_state 
                next_state 
                next_state 
                next_state <= Green;
        end case;
    end process;

    -- Add output logic process here
    -- Your code here
end Behavioral;

Hint

Use a process sensitive to current_state to set output signals. Use another process on clk rising edge to print the current state string using write and writeline.

Practice

1. In the three-process FSM coding style in VHDL, which process is responsible for storing the current state?

easy

A. The next state logic process

B. The state register process

C. The output logic process

D. The clock generation process

Solution

1. Step 1: Understand the role of each process

   The three-process FSM style divides the FSM into state register, next state logic, and output logic processes.

2. Step 2: Identify which process stores the current state

   The state register process updates and stores the current state on clock edges.

3. Final Answer:

   The state register process -> Option B

4. Quick Check:

   State storage = state register process [OK]

Hint: State storage always happens in the state register process [OK]

Common Mistakes:

• Confusing next state logic with state storage
• Thinking output logic stores the state
• Assuming clock generation is part of FSM

2. Which of the following is the correct sensitivity list for the next state logic process in a three-process FSM?

easy

A. clk, reset

B. clk

C. outputs

D. current_state, inputs

Solution

1. Step 1: Recall what next state logic depends on

   The next state logic calculates the next state based on the current state and inputs.

2. Step 2: Determine the sensitivity list

   It must react to changes in current_state and inputs, so these go in the sensitivity list.

3. Final Answer:

   current_state, inputs -> Option D

4. Quick Check:

   Next state logic sensitivity = current_state, inputs [OK]

Hint: Next state logic sensitive to current state and inputs only [OK]

Common Mistakes:

• Including clk in next state logic sensitivity list
• Using outputs in sensitivity list
• Leaving sensitivity list empty

3. Given the following partial FSM code snippet, what will be the output value of output_signal when current_state is S1 and input_signal is '1'?

process(current_state, input_signal)
begin
  case current_state is
    when S0 => output_signal <= '0';
    when S1 =>
      if input_signal = '1' then
        output_signal <= '1';
      else
        output_signal <= '0';
      end if;
    when others => output_signal <= '0';
  end case;
end process;

medium

A. Undefined

B. '0'

C. '1'

D. Signal retains previous value

Solution

1. Step 1: Analyze the output logic for state S1

   When current_state is S1, output_signal is '1' if input_signal is '1', else '0'.

2. Step 2: Apply given inputs

   current_state = S1 and input_signal = '1' means output_signal <= '1'.

3. Final Answer:

   '1' -> Option C

4. Quick Check:

   Output for S1 with input '1' = '1' [OK]

Hint: Check state and input conditions carefully for output logic [OK]

Common Mistakes:

• Ignoring input condition inside S1
• Assuming output is always '0' in S1
• Confusing output logic with next state logic

4. Identify the error in this state register process code snippet for a three-process FSM:

process(clk, reset)
begin
  if reset = '1' then
    current_state <= S0;
  elsif rising_edge(clk) then
    next_state <= current_state;
  end if;
end process;

medium

A. Using next_state instead of current_state on clock edge

B. Missing sensitivity to next_state signal

C. Reset condition should be inside rising_edge(clk)

D. No error, code is correct

Solution

1. Step 1: Understand state register role

   The state register updates current_state with next_state on clock edge.

2. Step 2: Check assignment inside clock edge

   The code assigns next_state <= current_state, which is reversed and wrong.

3. Final Answer:

   Using next_state instead of current_state on clock edge -> Option A

4. Quick Check:

   State register updates current_state, not next_state [OK]

Hint: State register updates current_state from next_state [OK]

Common Mistakes:

• Assigning next_state inside state register process
• Placing reset inside clock edge condition
• Confusing current_state and next_state signals

5. You want to design a three-process FSM with states IDLE, BUSY, and DONE. Which of the following correctly describes the responsibilities of the three processes?

hard

A. Process 1: Store current state; Process 2: Compute next state from current state and inputs; Process 3: Generate outputs based on current state

B. Process 1: Generate outputs; Process 2: Store current state; Process 3: Compute next state

C. Process 1: Compute next state; Process 2: Generate outputs; Process 3: Store current state

D. Process 1: Store current state and outputs; Process 2: Compute next state; Process 3: Reset FSM

Solution

1. Step 1: Recall three-process FSM roles

   The three processes are: state register (store current state), next state logic (compute next state), output logic (generate outputs).

2. Step 2: Match roles to options

   Process 1: Store current state; Process 2: Compute next state from current state and inputs; Process 3: Generate outputs based on current state correctly assigns these roles in order.

3. Final Answer:

   Process 1: Store current state; Process 2: Compute next state from current state and inputs; Process 3: Generate outputs based on current state -> Option A

4. Quick Check:

   Three-process FSM roles = B [OK]

Hint: Remember: register stores state, logic computes next, output drives signals [OK]

Common Mistakes:

• Mixing output generation with state storage
• Assigning reset to a separate process
• Combining multiple roles in one process