Why signed and unsigned arithmetic in VHDL? - Purpose & Use Cases

The Big Idea

What if your circuit could handle positive and negative numbers without you writing extra sign-checking code?

The Scenario

Imagine you are designing a digital circuit in VHDL that needs to handle both positive and negative numbers, like a calculator. You try to manually manage the signs and values using basic bit operations without special types.

The Problem

Doing arithmetic manually with plain bits is slow and error-prone. You must write extra code to check signs, handle overflows, and convert between positive and negative values. This makes your design complex and hard to debug.

The Solution

Using signed and unsigned arithmetic types in VHDL lets you work directly with numbers as positive or negative values. The language handles the details of addition, subtraction, and overflow for you, making your code simpler and more reliable.

Before vs After

✗ Before

signal a, b : std_logic_vector(7 downto 0);
signal result : std_logic_vector(7 downto 0);
-- manual bitwise addition with sign checks

✓ After

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
signal a, b : signed(7 downto 0);
signal result : signed(7 downto 0);
result <= a + b;

What It Enables

You can easily perform arithmetic on numbers with correct sign handling, enabling complex digital designs like signal processing or control systems.

Real Life Example

In a digital audio processor, signed arithmetic lets you add and subtract sound wave samples correctly, preserving the positive and negative amplitudes for clear sound output.

Key Takeaways

Manual bit operations for signed numbers are complex and error-prone.

Signed and unsigned types simplify arithmetic by handling signs automatically.

This leads to clearer, safer, and more maintainable VHDL code.

Practice

1. Which VHDL type should you use to correctly represent negative numbers in arithmetic operations?

easy

A. unsigned

B. signed

C. std_logic_vector

D. bit_vector

Solution

1. Step 1: Understand number representation types

   Signed types allow representation of both positive and negative numbers, unlike unsigned which only represent zero and positive numbers.

2. Step 2: Identify correct VHDL type for negatives

   In VHDL, the signed type from numeric_std is used for signed arithmetic, supporting negative values.

3. Final Answer:

   signed -> Option B

4. Quick Check:

   Negative numbers need signed type [OK]

Hint: Use signed type for negatives, unsigned for positives only [OK]

Common Mistakes:

• Using unsigned for negative numbers
• Using std_logic_vector without conversion
• Confusing bit_vector with numeric types

2. Which of the following is the correct way to declare a 4-bit unsigned signal in VHDL using numeric_std?

easy

A. signal data : signed(3 downto 0);

B. signal data : bit_vector(3 downto 0);

C. signal data : std_logic_vector(4 downto 0);

D. signal data : unsigned(3 downto 0);

Solution

1. Step 1: Identify the correct type for unsigned 4-bit signal

   The unsigned type from numeric_std is used for unsigned arithmetic and must have 4 bits indexed from 3 downto 0.

2. Step 2: Check each option

   signal data : signed(3 downto 0); uses signed type, which is for signed numbers. signal data : std_logic_vector(4 downto 0); has 5 bits (4 downto 0). signal data : bit_vector(3 downto 0); uses bit_vector, which is not numeric.

3. Final Answer:

   signal data : unsigned(3 downto 0); -> Option D

4. Quick Check:

   Unsigned 4-bit signal uses unsigned(3 downto 0) [OK]

Hint: Unsigned signals use unsigned type with correct bit range [OK]

Common Mistakes:

• Using signed instead of unsigned
• Incorrect bit range (off by one)
• Using std_logic_vector without conversion

3. Given the following VHDL code snippet, what is the decimal value of result after execution?

signal a : signed(3 downto 0) := "1101"; -- -3 in decimal
signal b : unsigned(3 downto 0) := "0011"; -- 3 in decimal
signal result : signed(4 downto 0);

result <= a + signed(resize(b, 5));

medium

A. 0

B. -6

C. 6

D. -3

Solution

1. Step 1: Convert signals to decimal

   a is signed "1101" which is -3 in decimal. b is unsigned "0011" which is 3 in decimal.

2. Step 2: Resize and add values

   b is resized to 5 bits and converted to signed, so 3 remains 3. Adding -3 + 3 = 0.

3. Final Answer:

   0 -> Option A

4. Quick Check:

   -3 + 3 = 0 [OK]

Hint: Convert both to signed before adding, then add values [OK]

Common Mistakes:

• Adding signed and unsigned directly without conversion
• Misinterpreting binary signed values
• Ignoring resize causing wrong bit width

4. Identify the error in the following VHDL code snippet:

signal x : signed(3 downto 0) := "0110";
signal y : unsigned(3 downto 0) := "0011";
signal z : signed(3 downto 0);
z <= x + y;

medium

A. Cannot add signed and unsigned directly without conversion

B. Signal z is declared with wrong bit range

C. Initialization of x is invalid binary

D. No error, code is correct

Solution

1. Step 1: Check types in addition

   In VHDL, you cannot add a signed and an unsigned type directly without converting one to the other's type.

2. Step 2: Identify missing conversion

   The code adds signed x and unsigned y directly, which causes a type mismatch error.

3. Final Answer:

   Cannot add signed and unsigned directly without conversion -> Option A

4. Quick Check:

   Signed + unsigned needs conversion [OK]

Hint: Convert unsigned to signed before adding to signed [OK]

Common Mistakes:

• Adding signed and unsigned without conversion
• Assuming std_logic_vector works for arithmetic
• Ignoring type mismatch errors

5. You want to subtract an unsigned 4-bit number b from a signed 5-bit number a in VHDL. Which is the correct way to perform this operation and store the result in a signed 6-bit signal result?

hard

A. result <= signed(a) - unsigned(b);

B. result <= a - b;

C. result <= resize(a, 6) - signed(resize(b, 6));

D. result <= resize(a, 5) - resize(b, 5);

Solution

1. Step 1: Understand type and size requirements

   To subtract unsigned b from signed a, both must be the same type and size. The result signal is 6 bits signed.

2. Step 2: Convert and resize operands properly

   Resize a to 6 bits signed, convert and resize b to signed 6 bits, then subtract.

3. Final Answer:

   result <= resize(a, 6) - signed(resize(b, 6)); -> Option C

4. Quick Check:

   Resize and convert unsigned to signed before subtracting [OK]

Hint: Resize both and convert unsigned to signed before subtracting [OK]

Common Mistakes:

• Subtracting without resizing operands
• Not converting unsigned to signed before subtraction
• Assigning result to smaller bit width