signed and unsigned arithmetic in VHDL - Step-by-Step Execution

Concept Flow - signed and unsigned arithmetic

Start

↓

Define signals: signed and unsigned

↓

Assign values

↓

Perform arithmetic operations

↓

Check result types

↓

Output results

↓

End

This flow shows how VHDL handles arithmetic with signed and unsigned types step-by-step.

Execution Sample

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

signal a : unsigned(3 downto 0) := "0110"; -- 6
signal b : signed(3 downto 0) := "1010";   -- -6
signal c : signed(4 downto 0);

c <= signed('0' & a) + b;

This code adds an unsigned 4-bit number and a signed 4-bit number by extending unsigned to signed and outputs a signed 5-bit result.

Execution Table

Step	Signal/Variable	Value	Operation	Result/Note
1	a	"0110"	Assign unsigned 6	a = 6 (unsigned)
2	b	"1010"	Assign signed -6	b = -6 (signed)
3	'0' & a	"00110"	Extend unsigned a to 5 bits	unsigned 6 extended to 5 bits
4	signed('0' & a)	"00110"	Convert extended unsigned to signed	signed 6
5	c	"00000"	Add signed 6 + signed -6	Result = 0 (signed 5 bits)
6	c	"00000"	Assign result to c	c = 0 (signed)

💡 Addition done, c holds signed 0 as result

Variable Tracker

Signal	Initial	After Step 3	After Step 5	Final
a	"0110" (6 unsigned)	"0110" (6 unsigned)	"0110" (6 unsigned)	"0110" (6 unsigned)
b	"1010" (-6 signed)	"1010" (-6 signed)	"1010" (-6 signed)	"1010" (-6 signed)
c	undefined	undefined	"00000" (0 signed)	"00000" (0 signed)

Key Moments - 3 Insights

Why do we add a '0' bit in front of the unsigned signal before converting to signed?

Adding '0' extends the unsigned number to one more bit to avoid overflow and to match the signed operand size, as shown in step 3 and 4 of the execution_table.

Why can't we add unsigned and signed signals directly without conversion?

Unsigned and signed types represent numbers differently; direct addition causes type mismatch errors. Conversion to a common type (signed here) is needed, as shown in step 4.

Why is the result signal 'c' declared as signed with one extra bit?

The extra bit allows the result to hold possible overflow and negative values from the addition, ensuring correct signed arithmetic, as seen in step 5 and 6.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of 'c' after the addition in step 5?

A "00110" (6 signed)

B "11110" (-2 signed)

C "00000" (0 signed)

D "10100" (-12 signed)

💡 Hint

Refer to step 5 and 6 in the execution_table where the addition result is shown.

At which step is the unsigned signal 'a' converted to signed?

A Step 4

B Step 2

C Step 3

D Step 5

💡 Hint

Check the operation column in execution_table for 'signed('0' & a)' conversion.

If we did not extend 'a' with a leading '0', what would happen?

A The addition would produce the same result.

B The addition would cause a type mismatch or overflow error.

C The result would be unsigned instead of signed.

D The signal 'b' would change value.

💡 Hint

Refer to key_moments about why extension is needed before conversion.

Concept Snapshot

VHDL signed and unsigned arithmetic:
- unsigned and signed are different types
- Convert unsigned to signed before arithmetic
- Extend bit width to avoid overflow
- Use ieee.numeric_std for arithmetic
- Result type should hold possible sign and size

Full Transcript

This example shows how to add an unsigned and a signed number in VHDL. First, the unsigned signal 'a' is extended by adding a leading zero bit to increase its size. Then it is converted to signed type to match the signed signal 'b'. The addition is performed on two signed signals, producing a signed result 'c' with one extra bit to hold the sum safely. The execution table traces each step: assigning values, extending and converting types, performing addition, and assigning the result. Key points include the need to convert types before arithmetic and to extend bit widths to avoid overflow or errors. The visual quiz tests understanding of these steps and their effects.

Practice

1. Which VHDL type should you use to correctly represent negative numbers in arithmetic operations?

easy

A. unsigned

B. signed

C. std_logic_vector

D. bit_vector

Solution

1. Step 1: Understand number representation types

   Signed types allow representation of both positive and negative numbers, unlike unsigned which only represent zero and positive numbers.

2. Step 2: Identify correct VHDL type for negatives

   In VHDL, the signed type from numeric_std is used for signed arithmetic, supporting negative values.

3. Final Answer:

   signed -> Option B

4. Quick Check:

   Negative numbers need signed type [OK]

Hint: Use signed type for negatives, unsigned for positives only [OK]

Common Mistakes:

• Using unsigned for negative numbers
• Using std_logic_vector without conversion
• Confusing bit_vector with numeric types

2. Which of the following is the correct way to declare a 4-bit unsigned signal in VHDL using numeric_std?

easy

A. signal data : signed(3 downto 0);

B. signal data : bit_vector(3 downto 0);

C. signal data : std_logic_vector(4 downto 0);

D. signal data : unsigned(3 downto 0);

Solution

1. Step 1: Identify the correct type for unsigned 4-bit signal

   The unsigned type from numeric_std is used for unsigned arithmetic and must have 4 bits indexed from 3 downto 0.

2. Step 2: Check each option

   signal data : signed(3 downto 0); uses signed type, which is for signed numbers. signal data : std_logic_vector(4 downto 0); has 5 bits (4 downto 0). signal data : bit_vector(3 downto 0); uses bit_vector, which is not numeric.

3. Final Answer:

   signal data : unsigned(3 downto 0); -> Option D

4. Quick Check:

   Unsigned 4-bit signal uses unsigned(3 downto 0) [OK]

Hint: Unsigned signals use unsigned type with correct bit range [OK]

Common Mistakes:

• Using signed instead of unsigned
• Incorrect bit range (off by one)
• Using std_logic_vector without conversion

3. Given the following VHDL code snippet, what is the decimal value of result after execution?

signal a : signed(3 downto 0) := "1101"; -- -3 in decimal
signal b : unsigned(3 downto 0) := "0011"; -- 3 in decimal
signal result : signed(4 downto 0);

result <= a + signed(resize(b, 5));

medium

A. 0

B. -6

C. 6

D. -3

Solution

1. Step 1: Convert signals to decimal

   a is signed "1101" which is -3 in decimal. b is unsigned "0011" which is 3 in decimal.

2. Step 2: Resize and add values

   b is resized to 5 bits and converted to signed, so 3 remains 3. Adding -3 + 3 = 0.

3. Final Answer:

   0 -> Option A

4. Quick Check:

   -3 + 3 = 0 [OK]

Hint: Convert both to signed before adding, then add values [OK]

Common Mistakes:

• Adding signed and unsigned directly without conversion
• Misinterpreting binary signed values
• Ignoring resize causing wrong bit width

4. Identify the error in the following VHDL code snippet:

signal x : signed(3 downto 0) := "0110";
signal y : unsigned(3 downto 0) := "0011";
signal z : signed(3 downto 0);
z <= x + y;

medium

A. Cannot add signed and unsigned directly without conversion

B. Signal z is declared with wrong bit range

C. Initialization of x is invalid binary

D. No error, code is correct

Solution

1. Step 1: Check types in addition

   In VHDL, you cannot add a signed and an unsigned type directly without converting one to the other's type.

2. Step 2: Identify missing conversion

   The code adds signed x and unsigned y directly, which causes a type mismatch error.

3. Final Answer:

   Cannot add signed and unsigned directly without conversion -> Option A

4. Quick Check:

   Signed + unsigned needs conversion [OK]

Hint: Convert unsigned to signed before adding to signed [OK]

Common Mistakes:

• Adding signed and unsigned without conversion
• Assuming std_logic_vector works for arithmetic
• Ignoring type mismatch errors

5. You want to subtract an unsigned 4-bit number b from a signed 5-bit number a in VHDL. Which is the correct way to perform this operation and store the result in a signed 6-bit signal result?

hard

A. result <= signed(a) - unsigned(b);

B. result <= a - b;

C. result <= resize(a, 6) - signed(resize(b, 6));

D. result <= resize(a, 5) - resize(b, 5);

Solution

1. Step 1: Understand type and size requirements

   To subtract unsigned b from signed a, both must be the same type and size. The result signal is 6 bits signed.

2. Step 2: Convert and resize operands properly

   Resize a to 6 bits signed, convert and resize b to signed 6 bits, then subtract.

3. Final Answer:

   result <= resize(a, 6) - signed(resize(b, 6)); -> Option C

4. Quick Check:

   Resize and convert unsigned to signed before subtracting [OK]

Hint: Resize both and convert unsigned to signed before subtracting [OK]

Common Mistakes:

• Subtracting without resizing operands
• Not converting unsigned to signed before subtraction
• Assigning result to smaller bit width