signed and unsigned arithmetic in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of signed addition in VHDL

What is the output of this VHDL process when adding two signed vectors?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test is
end entity;

architecture behavior of test is
  signal a, b, c : signed(3 downto 0);
begin
  process
  begin
    a <= to_signed(3, 4);
    b <= to_signed(-2, 4);
    wait for 10 ns;
    c <= a + b;
    wait;
  end process;
end architecture;

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test is
end entity;

architecture behavior of test is
  signal a, b, c : signed(3 downto 0);
begin
  process
  begin
    a <= to_signed(3, 4);
    b <= to_signed(-2, 4);
    wait for 10 ns;
    c <= a + b;
    wait;
  end process;
end architecture;

A c = "0010" (decimal 2)

B c = "1111" (decimal -1)

C c = "0001" (decimal 1)

D c = "0101" (decimal 5)

💡 Hint

Remember that signed vectors use two's complement representation.

Adding 3 and -2 results in 1. The 4-bit signed representation of 1 is "0001".

❓ Predict Output

intermediate

Unsigned subtraction result in VHDL

What is the value of signal c after this VHDL process runs?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test is
end entity;

architecture behavior of test is
  signal a, b, c : unsigned(3 downto 0);
begin
  process
  begin
    a <= to_unsigned(5, 4);
    b <= to_unsigned(3, 4);
    wait for 10 ns;
    c <= a - b;
    wait;
  end process;
end architecture;

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test is
end entity;

architecture behavior of test is
  signal a, b, c : unsigned(3 downto 0);
begin
  process
  begin
    a <= to_unsigned(5, 4);
    b <= to_unsigned(3, 4);
    wait for 10 ns;
    c <= a - b;
    wait;
  end process;
end architecture;

A c = "0010" (decimal 2)

B c = "1110" (decimal 14)

C c = "1000" (decimal 8)

D c = "0000" (decimal 0)

💡 Hint

Unsigned subtraction cannot represent negative numbers.

5 - 3 = 2, which is "0010" in 4-bit unsigned binary.

❓ Predict Output

advanced

Result of mixed signed and unsigned addition

What is the output of signal c after this VHDL process?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test is
end entity;

architecture behavior of test is
  signal a : signed(3 downto 0);
  signal b : unsigned(3 downto 0);
  signal c : signed(4 downto 0);
begin
  process
  begin
    a <= to_signed(-3, 4);
    b <= to_unsigned(5, 4);
    wait for 10 ns;
    c <= resize(a, 5) + signed(resize(b, 5));
    wait;
  end process;
end architecture;

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test is
end entity;

architecture behavior of test is
  signal a : signed(3 downto 0);
  signal b : unsigned(3 downto 0);
  signal c : signed(4 downto 0);
begin
  process
  begin
    a <= to_signed(-3, 4);
    b <= to_unsigned(5, 4);
    wait for 10 ns;
    c <= resize(a, 5) + signed(resize(b, 5));
    wait;
  end process;
end architecture;

A c = "11010" (decimal -6)

B c = "11110" (decimal -2)

C c = "00100" (decimal 4)

D c = "00010" (decimal 2)

💡 Hint

Convert unsigned to signed before adding, and consider bit width.

Resizing and converting unsigned 5 to signed 5-bit gives "00101" (5). Adding -3 ("11101" in 5 bits) plus 5 equals 2 ("00010").

❓ Predict Output

advanced

Overflow behavior in signed addition

What is the value of signal c after this VHDL process?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test is
end entity;

architecture behavior of test is
  signal a, b, c : signed(3 downto 0);
begin
  process
  begin
    a <= to_signed(7, 4);  -- max positive for 4-bit signed
    b <= to_signed(1, 4);
    wait for 10 ns;
    c <= a + b;
    wait;
  end process;
end architecture;

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test is
end entity;

architecture behavior of test is
  signal a, b, c : signed(3 downto 0);
begin
  process
  begin
    a <= to_signed(7, 4);  -- max positive for 4-bit signed
    b <= to_signed(1, 4);
    wait for 10 ns;
    c <= a + b;
    wait;
  end process;
end architecture;

A c = "0111" (decimal 7)

B c = "1000" (decimal -8, overflow occurred)

C c = "0000" (decimal 0)

D c = "1111" (decimal -1)

💡 Hint

4-bit signed addition can overflow and wrap around.

Adding 7 + 1 in 4-bit signed causes overflow, resulting in -8 ("1000").

🧠 Conceptual

expert

Error type from mixing signed and unsigned without conversion

What error will this VHDL code produce?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test is
end entity;

architecture behavior of test is
  signal a : signed(3 downto 0);
  signal b : unsigned(3 downto 0);
  signal c : signed(4 downto 0);
begin
  process
  begin
    a <= to_signed(2, 4);
    b <= to_unsigned(3, 4);
    wait for 10 ns;
    c <= resize(a, 5) + b;  -- no conversion of b to signed
    wait;
  end process;
end architecture;

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test is
end entity;

architecture behavior of test is
  signal a : signed(3 downto 0);
  signal b : unsigned(3 downto 0);
  signal c : signed(4 downto 0);
begin
  process
  begin
    a <= to_signed(2, 4);
    b <= to_unsigned(3, 4);
    wait for 10 ns;
    c <= resize(a, 5) + b;  -- no conversion of b to signed
    wait;
  end process;
end architecture;

A Type mismatch error: cannot add signed and unsigned directly

B Runtime error: signal c will have undefined value

C No error, c will be "00101" (decimal 5)

D Syntax error: missing semicolon

💡 Hint

Check the types of operands in the addition expression.

VHDL does not allow adding signed and unsigned types without explicit conversion, causing a type mismatch error.

Practice

1. Which VHDL type should you use to correctly represent negative numbers in arithmetic operations?

easy

A. unsigned

B. signed

C. std_logic_vector

D. bit_vector

Solution

1. Step 1: Understand number representation types

   Signed types allow representation of both positive and negative numbers, unlike unsigned which only represent zero and positive numbers.

2. Step 2: Identify correct VHDL type for negatives

   In VHDL, the signed type from numeric_std is used for signed arithmetic, supporting negative values.

3. Final Answer:

   signed -> Option B

4. Quick Check:

   Negative numbers need signed type [OK]

Hint: Use signed type for negatives, unsigned for positives only [OK]

Common Mistakes:

• Using unsigned for negative numbers
• Using std_logic_vector without conversion
• Confusing bit_vector with numeric types

2. Which of the following is the correct way to declare a 4-bit unsigned signal in VHDL using numeric_std?

easy

A. signal data : signed(3 downto 0);

B. signal data : bit_vector(3 downto 0);

C. signal data : std_logic_vector(4 downto 0);

D. signal data : unsigned(3 downto 0);

Solution

1. Step 1: Identify the correct type for unsigned 4-bit signal

   The unsigned type from numeric_std is used for unsigned arithmetic and must have 4 bits indexed from 3 downto 0.

2. Step 2: Check each option

   signal data : signed(3 downto 0); uses signed type, which is for signed numbers. signal data : std_logic_vector(4 downto 0); has 5 bits (4 downto 0). signal data : bit_vector(3 downto 0); uses bit_vector, which is not numeric.

3. Final Answer:

   signal data : unsigned(3 downto 0); -> Option D

4. Quick Check:

   Unsigned 4-bit signal uses unsigned(3 downto 0) [OK]

Hint: Unsigned signals use unsigned type with correct bit range [OK]

Common Mistakes:

• Using signed instead of unsigned
• Incorrect bit range (off by one)
• Using std_logic_vector without conversion

3. Given the following VHDL code snippet, what is the decimal value of result after execution?

signal a : signed(3 downto 0) := "1101"; -- -3 in decimal
signal b : unsigned(3 downto 0) := "0011"; -- 3 in decimal
signal result : signed(4 downto 0);

result <= a + signed(resize(b, 5));

medium

A. 0

B. -6

C. 6

D. -3

Solution

1. Step 1: Convert signals to decimal

   a is signed "1101" which is -3 in decimal. b is unsigned "0011" which is 3 in decimal.

2. Step 2: Resize and add values

   b is resized to 5 bits and converted to signed, so 3 remains 3. Adding -3 + 3 = 0.

3. Final Answer:

   0 -> Option A

4. Quick Check:

   -3 + 3 = 0 [OK]

Hint: Convert both to signed before adding, then add values [OK]

Common Mistakes:

• Adding signed and unsigned directly without conversion
• Misinterpreting binary signed values
• Ignoring resize causing wrong bit width

4. Identify the error in the following VHDL code snippet:

signal x : signed(3 downto 0) := "0110";
signal y : unsigned(3 downto 0) := "0011";
signal z : signed(3 downto 0);
z <= x + y;

medium

A. Cannot add signed and unsigned directly without conversion

B. Signal z is declared with wrong bit range

C. Initialization of x is invalid binary

D. No error, code is correct

Solution

1. Step 1: Check types in addition

   In VHDL, you cannot add a signed and an unsigned type directly without converting one to the other's type.

2. Step 2: Identify missing conversion

   The code adds signed x and unsigned y directly, which causes a type mismatch error.

3. Final Answer:

   Cannot add signed and unsigned directly without conversion -> Option A

4. Quick Check:

   Signed + unsigned needs conversion [OK]

Hint: Convert unsigned to signed before adding to signed [OK]

Common Mistakes:

• Adding signed and unsigned without conversion
• Assuming std_logic_vector works for arithmetic
• Ignoring type mismatch errors

5. You want to subtract an unsigned 4-bit number b from a signed 5-bit number a in VHDL. Which is the correct way to perform this operation and store the result in a signed 6-bit signal result?

hard

A. result <= signed(a) - unsigned(b);

B. result <= a - b;

C. result <= resize(a, 6) - signed(resize(b, 6));

D. result <= resize(a, 5) - resize(b, 5);

Solution

1. Step 1: Understand type and size requirements

   To subtract unsigned b from signed a, both must be the same type and size. The result signal is 6 bits signed.

2. Step 2: Convert and resize operands properly

   Resize a to 6 bits signed, convert and resize b to signed 6 bits, then subtract.

3. Final Answer:

   result <= resize(a, 6) - signed(resize(b, 6)); -> Option C

4. Quick Check:

   Resize and convert unsigned to signed before subtracting [OK]

Hint: Resize both and convert unsigned to signed before subtracting [OK]

Common Mistakes:

• Subtracting without resizing operands
• Not converting unsigned to signed before subtraction
• Assigning result to smaller bit width