signed and unsigned arithmetic in VHDL - Mini Project: Build & Apply

Signed and Unsigned Arithmetic in VHDL

📖 Scenario: You are designing a simple digital circuit that performs arithmetic operations on 4-bit numbers. Some numbers are signed (can be negative), and some are unsigned (only positive). You will write VHDL code to handle these numbers correctly.

🎯 Goal: Build a VHDL program that creates signed and unsigned 4-bit numbers, sets a threshold value, adds the numbers using the correct arithmetic type, and displays the result.

📋 What You'll Learn

Create a 4-bit unsigned number called u_num with value 9

Create a 4-bit signed number called s_num with value -3

Create an integer constant threshold with value 5

Add u_num and s_num as signed numbers and store in result

Print the result as an integer

💡 Why This Matters

🌍 Real World

Digital circuits often need to handle both signed and unsigned numbers, such as in signal processing or control systems.

💼 Career

Understanding signed and unsigned arithmetic in VHDL is essential for FPGA and ASIC design engineers working on hardware arithmetic units.

1

Create 4-bit unsigned and signed numbers

Create a 4-bit unsigned number called u_num with value 9 and a 4-bit signed number called s_num with value -3 using the unsigned and signed types from the ieee.numeric_std library.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ArithmeticExample is
end ArithmeticExample;

architecture Behavioral of ArithmeticExample is
    signal u_num : unsigned(3 downto 0);
    signal s_num : signed(3 downto 0);
    -- Your code here
begin
end Behavioral;

Hint

Use to_unsigned(9, 4) for the unsigned number and to_signed(-3, 4) for the signed number.

2

Add a threshold constant

Create an integer constant called threshold and set it to 5 inside the architecture.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ArithmeticExample is
end ArithmeticExample;

architecture Behavioral of ArithmeticExample is
    signal u_num : unsigned(3 downto 0) := to_unsigned(9, 4);
    signal s_num : signed(3 downto 0) := to_signed(-3, 4);
    constant threshold : integer := 5;
    -- Your code here
begin
end Behavioral;

Hint

Use constant threshold : integer := 5; inside the architecture.

3

Add the unsigned and signed numbers as signed

Create a signal called result of type signed(4 downto 0) and assign it the sum of s_num and signed(u_num) to add the unsigned number as signed. Use the correct type conversion.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ArithmeticExample is
end ArithmeticExample;

architecture Behavioral of ArithmeticExample is
    signal u_num : unsigned(3 downto 0) := to_unsigned(9, 4);
    signal s_num : signed(3 downto 0) := to_signed(-3, 4);
    constant threshold : integer := 5;
    signal result : signed(4 downto 0);
    -- Your code here
begin
    result <= resize(s_num, 5) + resize(signed(u_num), 5);
end Behavioral;

Hint

Use resize to make both numbers 5 bits before adding.

4

Print the result as integer

Add a process that prints the integer value of result using to_integer and report statement.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ArithmeticExample is
end ArithmeticExample;

architecture Behavioral of ArithmeticExample is
    signal u_num : unsigned(3 downto 0) := to_unsigned(9, 4);
    signal s_num : signed(3 downto 0) := to_signed(-3, 4);
    constant threshold : integer := 5;
    signal result : signed(4 downto 0);
begin
    result <= resize(s_num, 5) + resize(signed(u_num), 5);

    process
    begin
        -- Your code here
    end process;
end Behavioral;

Hint

Use report "Result is: " & integer'image(to_integer(result)); inside a process.

Practice

1. Which VHDL type should you use to correctly represent negative numbers in arithmetic operations?

easy

A. unsigned

B. signed

C. std_logic_vector

D. bit_vector

Solution

1. Step 1: Understand number representation types

   Signed types allow representation of both positive and negative numbers, unlike unsigned which only represent zero and positive numbers.

2. Step 2: Identify correct VHDL type for negatives

   In VHDL, the signed type from numeric_std is used for signed arithmetic, supporting negative values.

3. Final Answer:

   signed -> Option B

4. Quick Check:

   Negative numbers need signed type [OK]

Hint: Use signed type for negatives, unsigned for positives only [OK]

Common Mistakes:

• Using unsigned for negative numbers
• Using std_logic_vector without conversion
• Confusing bit_vector with numeric types

2. Which of the following is the correct way to declare a 4-bit unsigned signal in VHDL using numeric_std?

easy

A. signal data : signed(3 downto 0);

B. signal data : bit_vector(3 downto 0);

C. signal data : std_logic_vector(4 downto 0);

D. signal data : unsigned(3 downto 0);

Solution

1. Step 1: Identify the correct type for unsigned 4-bit signal

   The unsigned type from numeric_std is used for unsigned arithmetic and must have 4 bits indexed from 3 downto 0.

2. Step 2: Check each option

   signal data : signed(3 downto 0); uses signed type, which is for signed numbers. signal data : std_logic_vector(4 downto 0); has 5 bits (4 downto 0). signal data : bit_vector(3 downto 0); uses bit_vector, which is not numeric.

3. Final Answer:

   signal data : unsigned(3 downto 0); -> Option D

4. Quick Check:

   Unsigned 4-bit signal uses unsigned(3 downto 0) [OK]

Hint: Unsigned signals use unsigned type with correct bit range [OK]

Common Mistakes:

• Using signed instead of unsigned
• Incorrect bit range (off by one)
• Using std_logic_vector without conversion

3. Given the following VHDL code snippet, what is the decimal value of result after execution?

signal a : signed(3 downto 0) := "1101"; -- -3 in decimal
signal b : unsigned(3 downto 0) := "0011"; -- 3 in decimal
signal result : signed(4 downto 0);

result <= a + signed(resize(b, 5));

medium

A. 0

B. -6

C. 6

D. -3

Solution

1. Step 1: Convert signals to decimal

   a is signed "1101" which is -3 in decimal. b is unsigned "0011" which is 3 in decimal.

2. Step 2: Resize and add values

   b is resized to 5 bits and converted to signed, so 3 remains 3. Adding -3 + 3 = 0.

3. Final Answer:

   0 -> Option A

4. Quick Check:

   -3 + 3 = 0 [OK]

Hint: Convert both to signed before adding, then add values [OK]

Common Mistakes:

• Adding signed and unsigned directly without conversion
• Misinterpreting binary signed values
• Ignoring resize causing wrong bit width

4. Identify the error in the following VHDL code snippet:

signal x : signed(3 downto 0) := "0110";
signal y : unsigned(3 downto 0) := "0011";
signal z : signed(3 downto 0);
z <= x + y;

medium

A. Cannot add signed and unsigned directly without conversion

B. Signal z is declared with wrong bit range

C. Initialization of x is invalid binary

D. No error, code is correct

Solution

1. Step 1: Check types in addition

   In VHDL, you cannot add a signed and an unsigned type directly without converting one to the other's type.

2. Step 2: Identify missing conversion

   The code adds signed x and unsigned y directly, which causes a type mismatch error.

3. Final Answer:

   Cannot add signed and unsigned directly without conversion -> Option A

4. Quick Check:

   Signed + unsigned needs conversion [OK]

Hint: Convert unsigned to signed before adding to signed [OK]

Common Mistakes:

• Adding signed and unsigned without conversion
• Assuming std_logic_vector works for arithmetic
• Ignoring type mismatch errors

5. You want to subtract an unsigned 4-bit number b from a signed 5-bit number a in VHDL. Which is the correct way to perform this operation and store the result in a signed 6-bit signal result?

hard

A. result <= signed(a) - unsigned(b);

B. result <= a - b;

C. result <= resize(a, 6) - signed(resize(b, 6));

D. result <= resize(a, 5) - resize(b, 5);

Solution

1. Step 1: Understand type and size requirements

   To subtract unsigned b from signed a, both must be the same type and size. The result signal is 6 bits signed.

2. Step 2: Convert and resize operands properly

   Resize a to 6 bits signed, convert and resize b to signed 6 bits, then subtract.

3. Final Answer:

   result <= resize(a, 6) - signed(resize(b, 6)); -> Option C

4. Quick Check:

   Resize and convert unsigned to signed before subtracting [OK]

Hint: Resize both and convert unsigned to signed before subtracting [OK]

Common Mistakes:

• Subtracting without resizing operands
• Not converting unsigned to signed before subtraction
• Assigning result to smaller bit width