Process sensitivity list in VHDL - Step-by-Step Execution

Concept Flow - Process sensitivity list

Start simulation

↓

Signal changes?

Yes↓

Check sensitivity list

↓

Update outputs

↓

Wait for next signal change

The process runs only when a signal in its sensitivity list changes. Changes to other signals do not trigger the process.

Execution Sample

VHDL

process(clk, reset)
begin
  if reset = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

This process triggers only when clk or reset changes, updating q accordingly.

Execution Table

Step	Signal Changed	In Sensitivity List?	Process Runs?	Action	Output q
1	reset = '0' to '1'	Yes	Yes	q <= '0'	'0'
2	reset = '1' to '0'	Yes	Yes	No reset, wait for clk	'0'
3	d changes	No	No	Process ignored	'0'
4	clk rising edge	Yes	Yes	q <= d (assume d='1')	'1'
5	clk falling edge	Yes	Yes	No action (no rising edge)	'1'
6	d changes to '0'	No	No	Process ignored	'1'
7	clk rising edge	Yes	Yes	q <= d (assume d='0')	'0'

💡 Process only runs when signals in sensitivity list (clk, reset) change.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	After Step 4	After Step 5	After Step 6	After Step 7
reset	'0'	'1'	'0'	'0'	'0'	'0'	'0'	'0'
clk	'0'	'0'	'0'	'0'	'1' (rising)	'0' (falling)	'0'	'1' (rising)
d	'0'	'0'	'0'	'1'	'1'	'1'	'0'	'0'
q	'0'	'0'	'0'	'0'	'1'	'1'	'1'	'0'

Key Moments - 3 Insights

Why does the process not run when signal 'd' changes at step 3?

Because 'd' is not in the sensitivity list (see execution_table step 3), the process ignores changes to 'd' and does not run.

Why does the process run on both rising and falling edges of clk but only update q on rising edge?

The process triggers on any clk change (in sensitivity list), but inside it updates q only on rising_edge(clk) (see execution_table steps 4 and 5).

What happens if a signal not in the sensitivity list changes?

The process does not run and ignores that change (see execution_table steps 3 and 6).

Visual Quiz - 3 Questions

Look at the execution table, what is the value of q after step 4?

A '1'

B '0'

C 'd'

D Unchanged

💡 Hint

Check the 'Output q' column at step 4 in the execution_table.

At which step does the process ignore a signal change because it is not in the sensitivity list?

A Step 1

B Step 2

C Step 3

D Step 6

💡 Hint

Look for 'Process ignored' in the 'Action' column in execution_table.

If we add 'd' to the sensitivity list, what would change in the execution table?

A Output q would never change

B Process would run at step 3

C Process would ignore step 2 still

D Process would run only on reset changes

💡 Hint

Adding 'd' means process triggers on 'd' changes; check step 3 behavior.

Concept Snapshot

process (sensitivity_list) begin
  -- code runs only when signals in sensitivity_list change
  if reset = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

Key: Process triggers only on sensitivity list signals changing, ignoring others.

Full Transcript

A VHDL process with a sensitivity list runs only when one of the listed signals changes. For example, a process sensitive to clk and reset runs when clk or reset changes, but not when other signals like d change. Inside the process, conditions like rising_edge(clk) control when outputs update. The execution table shows steps where signals change, whether the process runs, and how output q updates. Changes to signals not in the sensitivity list do not trigger the process. This helps design efficient hardware behavior.

Practice

1. What does the sensitivity list in a VHDL process specify?

easy

A. Which signals trigger the process to run when they change

B. The order in which signals are assigned values

C. The data types of signals inside the process

D. The clock frequency for the process execution

Solution

1. Step 1: Understand the role of sensitivity list

   The sensitivity list tells VHDL which signals to watch for changes.

2. Step 2: Identify what triggers the process

   The process runs only when a signal in the sensitivity list changes value.

3. Final Answer:

   Which signals trigger the process to run when they change -> Option A

4. Quick Check:

   Sensitivity list = triggers process run [OK]

Hint: Sensitivity list = signals that start the process [OK]

Common Mistakes:

• Thinking sensitivity list sets signal data types
• Confusing sensitivity list with signal assignment order
• Assuming sensitivity list controls clock frequency

2. Which of the following is the correct syntax for a process sensitivity list in VHDL?

easy

A. process {clk, reset}

B. process clk, reset

C. process [clk, reset]

D. process(clk, reset)

Solution

1. Step 1: Recall VHDL process syntax

   The sensitivity list is enclosed in parentheses after the keyword process.

2. Step 2: Match correct syntax

   Only the syntax with parentheses and comma-separated signals is correct: process(clk, reset)

3. Final Answer:

   process(clk, reset) -> Option D

4. Quick Check:

   Parentheses and commas = correct syntax [OK]

Hint: Use parentheses with commas for sensitivity list [OK]

Common Mistakes:

• Omitting parentheses around sensitivity list
• Using square or curly brackets instead of parentheses
• Separating signals with spaces instead of commas

3. Consider this VHDL process:

process(a, b)
begin
  c <= a and b;
end process;

What happens if signal b changes value?

medium

A. The process does not run because only a triggers it

B. The process runs and updates c

C. The process runs but c remains unchanged

D. The process causes a syntax error

Solution

1. Step 1: Check sensitivity list signals

   The process sensitivity list includes signals a and b.

2. Step 2: Understand process triggering

   When b changes, the process runs and updates c with a and b.

3. Final Answer:

   The process runs and updates c -> Option B

4. Quick Check:

   Signal in sensitivity list changed = process runs [OK]

Hint: Process runs when any sensitivity signal changes [OK]

Common Mistakes:

• Thinking only first signal triggers process
• Assuming process runs but output doesn't update
• Confusing syntax error with normal behavior

4. Identify the error in this VHDL process:

process(clk)
begin
  if reset = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

Assuming reset is a signal, what is the problem?

medium

A. Reset signal is missing from the sensitivity list

B. Clock signal should not be in the sensitivity list

C. The process should use falling_edge instead of rising_edge

D. The process syntax is correct with no errors

Solution

1. Step 1: Check signals used inside process

   The process uses reset and clk signals.

2. Step 2: Verify sensitivity list completeness

   Only clk is in the sensitivity list; reset is missing, which can cause simulation mismatches.

3. Final Answer:

   Reset signal is missing from the sensitivity list -> Option A

4. Quick Check:

   All input signals must be in sensitivity list [OK]

Hint: Include all input signals in sensitivity list [OK]

Common Mistakes:

• Ignoring signals that affect outputs in sensitivity list
• Thinking clock should be removed from sensitivity list
• Confusing edge detection with sensitivity list content

5. You have a process sensitive to signals a and b. Inside, you compute c <= a or b;. Later, you add a new signal enable that gates the output: if enable = '1' then c <= a or b; else c <= '0'; end if;
What must you do to the sensitivity list to ensure correct simulation?

hard

A. Remove a and b from the sensitivity list

B. No change needed; sensitivity list stays the same

C. Add enable to the sensitivity list

D. Replace sensitivity list with only enable

Solution

1. Step 1: Identify all signals affecting outputs

   Now enable controls output c along with a and b.

2. Step 2: Update sensitivity list accordingly

   To simulate correctly, enable must be added to the sensitivity list with a and b.

3. Final Answer:

   Add enable to the sensitivity list -> Option C

4. Quick Check:

   All input signals in sensitivity list = correct simulation [OK]

Hint: Add all signals that affect outputs to sensitivity list [OK]

Common Mistakes:

• Forgetting to add new control signals to sensitivity list
• Removing original signals from sensitivity list incorrectly
• Assuming sensitivity list auto-updates with code changes