Process sensitivity list in VHDL - Mini Project: Build & Apply

Understanding Process Sensitivity List in VHDL

📖 Scenario: You are designing a simple digital circuit in VHDL that reacts to changes in input signals. To make your design efficient, you need to use a process with a sensitivity list that triggers only when specific signals change.

🎯 Goal: Build a VHDL process that uses a sensitivity list to update an output signal whenever one of the input signals changes.

📋 What You'll Learn

Create input signals a and b of type std_logic

Create an output signal c of type std_logic

Write a process with a sensitivity list containing a and b

Inside the process, assign c the logical AND of a and b

Print the value of c after the process

💡 Why This Matters

🌍 Real World

Using process sensitivity lists helps digital circuits respond efficiently to input changes, saving power and improving performance.

💼 Career

Understanding process sensitivity lists is essential for hardware engineers and FPGA designers to write clean and efficient VHDL code.

1

Create input and output signals

Create signals a and b of type std_logic and an output signal c of type std_logic inside an architecture.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SimpleAnd is
    Port ();
end SimpleAnd;

architecture Behavioral of SimpleAnd is
    -- Declare signals a, b, and c here
    -- Your code here
begin

end Behavioral;

Hint

Use signal keyword to declare a, b, and c inside the architecture.

2

Add a process with sensitivity list

Add a process inside the architecture with a sensitivity list containing a and b.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SimpleAnd is
    Port ();
end SimpleAnd;

architecture Behavioral of SimpleAnd is
    signal a : std_logic := '0';
    signal b : std_logic := '0';
    signal c : std_logic := '0';
begin
    -- Add a process with sensitivity list (a, b) here
    -- Your code here
end Behavioral;

Hint

Write process(a, b) to start the process with sensitivity list.

3

Assign output inside the process

Inside the process, assign c the logical AND of a and b using the and operator.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SimpleAnd is
    Port ();
end SimpleAnd;

architecture Behavioral of SimpleAnd is
    signal a : std_logic := '0';
    signal b : std_logic := '0';
    signal c : std_logic := '0';
begin
    process(a, b)
    begin
        -- Assign c the logical AND of a and b here
        -- Your code here
    end process;
end Behavioral;

Hint

Use the assignment operator <= inside the process to assign c.

4

Print the output signal value

Add a simple report statement after the process to print the value of c using report and std_logic'image conversion.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SimpleAnd is
    Port ();
end SimpleAnd;

architecture Behavioral of SimpleAnd is
    signal a : std_logic := '0';
    signal b : std_logic := '0';
    signal c : std_logic := '0';
begin
    process(a, b)
    begin
        c <= a and b;
    end process;

    -- Add a report statement to print c here
    -- Your code here
end Behavioral;

Hint

Use report "Value of c is " & std_logic'image(c); to print the value of c.

Practice

1. What does the sensitivity list in a VHDL process specify?

easy

A. Which signals trigger the process to run when they change

B. The order in which signals are assigned values

C. The data types of signals inside the process

D. The clock frequency for the process execution

Solution

1. Step 1: Understand the role of sensitivity list

   The sensitivity list tells VHDL which signals to watch for changes.

2. Step 2: Identify what triggers the process

   The process runs only when a signal in the sensitivity list changes value.

3. Final Answer:

   Which signals trigger the process to run when they change -> Option A

4. Quick Check:

   Sensitivity list = triggers process run [OK]

Hint: Sensitivity list = signals that start the process [OK]

Common Mistakes:

• Thinking sensitivity list sets signal data types
• Confusing sensitivity list with signal assignment order
• Assuming sensitivity list controls clock frequency

2. Which of the following is the correct syntax for a process sensitivity list in VHDL?

easy

A. process {clk, reset}

B. process clk, reset

C. process [clk, reset]

D. process(clk, reset)

Solution

1. Step 1: Recall VHDL process syntax

   The sensitivity list is enclosed in parentheses after the keyword process.

2. Step 2: Match correct syntax

   Only the syntax with parentheses and comma-separated signals is correct: process(clk, reset)

3. Final Answer:

   process(clk, reset) -> Option D

4. Quick Check:

   Parentheses and commas = correct syntax [OK]

Hint: Use parentheses with commas for sensitivity list [OK]

Common Mistakes:

• Omitting parentheses around sensitivity list
• Using square or curly brackets instead of parentheses
• Separating signals with spaces instead of commas

3. Consider this VHDL process:

process(a, b)
begin
  c <= a and b;
end process;

What happens if signal b changes value?

medium

A. The process does not run because only a triggers it

B. The process runs and updates c

C. The process runs but c remains unchanged

D. The process causes a syntax error

Solution

1. Step 1: Check sensitivity list signals

   The process sensitivity list includes signals a and b.

2. Step 2: Understand process triggering

   When b changes, the process runs and updates c with a and b.

3. Final Answer:

   The process runs and updates c -> Option B

4. Quick Check:

   Signal in sensitivity list changed = process runs [OK]

Hint: Process runs when any sensitivity signal changes [OK]

Common Mistakes:

• Thinking only first signal triggers process
• Assuming process runs but output doesn't update
• Confusing syntax error with normal behavior

4. Identify the error in this VHDL process:

process(clk)
begin
  if reset = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

Assuming reset is a signal, what is the problem?

medium

A. Reset signal is missing from the sensitivity list

B. Clock signal should not be in the sensitivity list

C. The process should use falling_edge instead of rising_edge

D. The process syntax is correct with no errors

Solution

1. Step 1: Check signals used inside process

   The process uses reset and clk signals.

2. Step 2: Verify sensitivity list completeness

   Only clk is in the sensitivity list; reset is missing, which can cause simulation mismatches.

3. Final Answer:

   Reset signal is missing from the sensitivity list -> Option A

4. Quick Check:

   All input signals must be in sensitivity list [OK]

Hint: Include all input signals in sensitivity list [OK]

Common Mistakes:

• Ignoring signals that affect outputs in sensitivity list
• Thinking clock should be removed from sensitivity list
• Confusing edge detection with sensitivity list content

5. You have a process sensitive to signals a and b. Inside, you compute c <= a or b;. Later, you add a new signal enable that gates the output: if enable = '1' then c <= a or b; else c <= '0'; end if;
What must you do to the sensitivity list to ensure correct simulation?

hard

A. Remove a and b from the sensitivity list

B. No change needed; sensitivity list stays the same

C. Add enable to the sensitivity list

D. Replace sensitivity list with only enable

Solution

1. Step 1: Identify all signals affecting outputs

   Now enable controls output c along with a and b.

2. Step 2: Update sensitivity list accordingly

   To simulate correctly, enable must be added to the sensitivity list with a and b.

3. Final Answer:

   Add enable to the sensitivity list -> Option C

4. Quick Check:

   All input signals in sensitivity list = correct simulation [OK]

Hint: Add all signals that affect outputs to sensitivity list [OK]

Common Mistakes:

• Forgetting to add new control signals to sensitivity list
• Removing original signals from sensitivity list incorrectly
• Assuming sensitivity list auto-updates with code changes