Process sensitivity list in VHDL - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a process sensitivity list in VHDL?

A process sensitivity list is a list of signals that trigger the process to run whenever any of those signals change value.

beginner

Why do we use a sensitivity list in a VHDL process?

We use a sensitivity list to tell the simulator which signals to watch. When any signal in the list changes, the process runs, making simulation efficient.

intermediate

What happens if a signal that affects the process is missing from the sensitivity list?

The process will not run when that signal changes, which can cause incorrect or unexpected behavior in the simulation.

beginner

How do you write a process with a sensitivity list for signals 'clk' and 'reset'?

process(clk, reset) is begin -- process code here end process;

intermediate

Can a process have an empty sensitivity list in VHDL?

No, a process must have at least one signal in its sensitivity list or use a wait statement inside to control execution.

What triggers a VHDL process to execute?

A Manual user input

B A change in any variable inside the process

C A change in any signal in the sensitivity list

D Only the clock signal

A process runs whenever any signal in its sensitivity list changes value.

Which of the following is a correct sensitivity list syntax?

A process [clk, reset]

B process clk, reset

C process {clk, reset}

D process(clk, reset)

The correct syntax uses parentheses with signals separated by commas.

What happens if you omit a signal from the sensitivity list that the process depends on?

A The process will not run when that signal changes

B The process runs twice as fast

C The process ignores all signals

D The process runs continuously

Missing signals in the sensitivity list cause the process to miss changes and not run as expected.

Can a process without a sensitivity list run in VHDL?

A No, it will cause a syntax error

B Yes, if it contains a wait statement

C Yes, it runs automatically every cycle

D No, processes must always have sensitivity lists

Processes without sensitivity lists must use wait statements to control execution.

Which signals should be included in a process sensitivity list?

A All signals read inside the process

B Only output signals

C Only clock signals

D Only signals assigned inside the process

All signals that the process reads and depends on should be in the sensitivity list.

Explain what a process sensitivity list is and why it is important in VHDL.

Think about what makes a process run in simulation.

Describe what could go wrong if a signal used inside a process is not included in the sensitivity list.

Consider what happens when the process misses changes.

Practice

1. What does the sensitivity list in a VHDL process specify?

easy

A. Which signals trigger the process to run when they change

B. The order in which signals are assigned values

C. The data types of signals inside the process

D. The clock frequency for the process execution

Solution

1. Step 1: Understand the role of sensitivity list

   The sensitivity list tells VHDL which signals to watch for changes.

2. Step 2: Identify what triggers the process

   The process runs only when a signal in the sensitivity list changes value.

3. Final Answer:

   Which signals trigger the process to run when they change -> Option A

4. Quick Check:

   Sensitivity list = triggers process run [OK]

Hint: Sensitivity list = signals that start the process [OK]

Common Mistakes:

• Thinking sensitivity list sets signal data types
• Confusing sensitivity list with signal assignment order
• Assuming sensitivity list controls clock frequency

2. Which of the following is the correct syntax for a process sensitivity list in VHDL?

easy

A. process {clk, reset}

B. process clk, reset

C. process [clk, reset]

D. process(clk, reset)

Solution

1. Step 1: Recall VHDL process syntax

   The sensitivity list is enclosed in parentheses after the keyword process.

2. Step 2: Match correct syntax

   Only the syntax with parentheses and comma-separated signals is correct: process(clk, reset)

3. Final Answer:

   process(clk, reset) -> Option D

4. Quick Check:

   Parentheses and commas = correct syntax [OK]

Hint: Use parentheses with commas for sensitivity list [OK]

Common Mistakes:

• Omitting parentheses around sensitivity list
• Using square or curly brackets instead of parentheses
• Separating signals with spaces instead of commas

3. Consider this VHDL process:

process(a, b)
begin
  c <= a and b;
end process;

What happens if signal b changes value?

medium

A. The process does not run because only a triggers it

B. The process runs and updates c

C. The process runs but c remains unchanged

D. The process causes a syntax error

Solution

1. Step 1: Check sensitivity list signals

   The process sensitivity list includes signals a and b.

2. Step 2: Understand process triggering

   When b changes, the process runs and updates c with a and b.

3. Final Answer:

   The process runs and updates c -> Option B

4. Quick Check:

   Signal in sensitivity list changed = process runs [OK]

Hint: Process runs when any sensitivity signal changes [OK]

Common Mistakes:

• Thinking only first signal triggers process
• Assuming process runs but output doesn't update
• Confusing syntax error with normal behavior

4. Identify the error in this VHDL process:

process(clk)
begin
  if reset = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

Assuming reset is a signal, what is the problem?

medium

A. Reset signal is missing from the sensitivity list

B. Clock signal should not be in the sensitivity list

C. The process should use falling_edge instead of rising_edge

D. The process syntax is correct with no errors

Solution

1. Step 1: Check signals used inside process

   The process uses reset and clk signals.

2. Step 2: Verify sensitivity list completeness

   Only clk is in the sensitivity list; reset is missing, which can cause simulation mismatches.

3. Final Answer:

   Reset signal is missing from the sensitivity list -> Option A

4. Quick Check:

   All input signals must be in sensitivity list [OK]

Hint: Include all input signals in sensitivity list [OK]

Common Mistakes:

• Ignoring signals that affect outputs in sensitivity list
• Thinking clock should be removed from sensitivity list
• Confusing edge detection with sensitivity list content

5. You have a process sensitive to signals a and b. Inside, you compute c <= a or b;. Later, you add a new signal enable that gates the output: if enable = '1' then c <= a or b; else c <= '0'; end if;
What must you do to the sensitivity list to ensure correct simulation?

hard

A. Remove a and b from the sensitivity list

B. No change needed; sensitivity list stays the same

C. Add enable to the sensitivity list

D. Replace sensitivity list with only enable

Solution

1. Step 1: Identify all signals affecting outputs

   Now enable controls output c along with a and b.

2. Step 2: Update sensitivity list accordingly

   To simulate correctly, enable must be added to the sensitivity list with a and b.

3. Final Answer:

   Add enable to the sensitivity list -> Option C

4. Quick Check:

   All input signals in sensitivity list = correct simulation [OK]

Hint: Add all signals that affect outputs to sensitivity list [OK]

Common Mistakes:

• Forgetting to add new control signals to sensitivity list
• Removing original signals from sensitivity list incorrectly
• Assuming sensitivity list auto-updates with code changes