Process sensitivity list in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to add the correct signal to the process sensitivity list.

VHDL

process([1])
begin
  -- process body
end process;

Drag options to blanks, or click blank then click option'

Adata

Benable

Creset

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Including data signals instead of the clock in the sensitivity list.

Leaving the sensitivity list empty.

The sensitivity list should include the clock signal clk to trigger the process on clock edges.

2fill in blank

medium

Complete the code to include both signals in the sensitivity list.

VHDL

process([1])
begin
  -- process body
end process;

Drag options to blanks, or click blank then click option'

Aclk, reset

Bdata, enable

Cclk, data

Dreset, enable

Attempts:

3 left

💡 Hint

Common Mistakes

Including only the clock or only the reset signal.

Including unrelated signals like enable.

The process should be sensitive to both clk and reset signals to handle synchronous reset logic.

3fill in blank

hard

Fix the error in the sensitivity list by choosing the correct signal.

VHDL

process([1])
begin
  if rising_edge(clk) then
    -- process body
  end if;
end process;

Drag options to blanks, or click blank then click option'

Adata

Breset

Cclk

Denable

Attempts:

3 left

💡 Hint

Common Mistakes

Using a data signal instead of the clock in the sensitivity list.

Omitting the clock signal.

The sensitivity list must include the clock signal clk when using rising_edge(clk) inside the process.

4fill in blank

hard

Fill both blanks to complete the sensitivity list for asynchronous reset and clock.

VHDL

process([1], [2])
begin
  if [1] = '1' then
    -- reset logic
  elsif rising_edge([2]) then
    -- clocked logic
  end if;
end process;

Drag options to blanks, or click blank then click option'

Areset

Bclk

Cenable

Ddata

Attempts:

3 left

💡 Hint

Common Mistakes

Swapping the order of reset and clock signals.

Including unrelated signals like enable or data.

The sensitivity list must include reset for asynchronous reset and clk for clocked logic.

5fill in blank

hard

Fill all three blanks to complete the process sensitivity list and conditions for asynchronous reset and clock edge.

VHDL

process([1], [2], [3])
begin
  if [1] = '1' then
    -- async reset logic
  elsif rising_edge([2]) then
    -- clocked logic
  end if;
end process;

Drag options to blanks, or click blank then click option'

Areset_n

Bclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using active high reset signal name instead of active low.

Mixing up the order of signals in the sensitivity list.

The sensitivity list includes reset_n and clk. The first blank in the if condition is reset_n, and the rising_edge uses clk.

Practice

1. What does the sensitivity list in a VHDL process specify?

easy

A. Which signals trigger the process to run when they change

B. The order in which signals are assigned values

C. The data types of signals inside the process

D. The clock frequency for the process execution

Solution

1. Step 1: Understand the role of sensitivity list

   The sensitivity list tells VHDL which signals to watch for changes.

2. Step 2: Identify what triggers the process

   The process runs only when a signal in the sensitivity list changes value.

3. Final Answer:

   Which signals trigger the process to run when they change -> Option A

4. Quick Check:

   Sensitivity list = triggers process run [OK]

Hint: Sensitivity list = signals that start the process [OK]

Common Mistakes:

• Thinking sensitivity list sets signal data types
• Confusing sensitivity list with signal assignment order
• Assuming sensitivity list controls clock frequency

2. Which of the following is the correct syntax for a process sensitivity list in VHDL?

easy

A. process {clk, reset}

B. process clk, reset

C. process [clk, reset]

D. process(clk, reset)

Solution

1. Step 1: Recall VHDL process syntax

   The sensitivity list is enclosed in parentheses after the keyword process.

2. Step 2: Match correct syntax

   Only the syntax with parentheses and comma-separated signals is correct: process(clk, reset)

3. Final Answer:

   process(clk, reset) -> Option D

4. Quick Check:

   Parentheses and commas = correct syntax [OK]

Hint: Use parentheses with commas for sensitivity list [OK]

Common Mistakes:

• Omitting parentheses around sensitivity list
• Using square or curly brackets instead of parentheses
• Separating signals with spaces instead of commas

3. Consider this VHDL process:

process(a, b)
begin
  c <= a and b;
end process;

What happens if signal b changes value?

medium

A. The process does not run because only a triggers it

B. The process runs and updates c

C. The process runs but c remains unchanged

D. The process causes a syntax error

Solution

1. Step 1: Check sensitivity list signals

   The process sensitivity list includes signals a and b.

2. Step 2: Understand process triggering

   When b changes, the process runs and updates c with a and b.

3. Final Answer:

   The process runs and updates c -> Option B

4. Quick Check:

   Signal in sensitivity list changed = process runs [OK]

Hint: Process runs when any sensitivity signal changes [OK]

Common Mistakes:

• Thinking only first signal triggers process
• Assuming process runs but output doesn't update
• Confusing syntax error with normal behavior

4. Identify the error in this VHDL process:

process(clk)
begin
  if reset = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

Assuming reset is a signal, what is the problem?

medium

A. Reset signal is missing from the sensitivity list

B. Clock signal should not be in the sensitivity list

C. The process should use falling_edge instead of rising_edge

D. The process syntax is correct with no errors

Solution

1. Step 1: Check signals used inside process

   The process uses reset and clk signals.

2. Step 2: Verify sensitivity list completeness

   Only clk is in the sensitivity list; reset is missing, which can cause simulation mismatches.

3. Final Answer:

   Reset signal is missing from the sensitivity list -> Option A

4. Quick Check:

   All input signals must be in sensitivity list [OK]

Hint: Include all input signals in sensitivity list [OK]

Common Mistakes:

• Ignoring signals that affect outputs in sensitivity list
• Thinking clock should be removed from sensitivity list
• Confusing edge detection with sensitivity list content

5. You have a process sensitive to signals a and b. Inside, you compute c <= a or b;. Later, you add a new signal enable that gates the output: if enable = '1' then c <= a or b; else c <= '0'; end if;
What must you do to the sensitivity list to ensure correct simulation?

hard

A. Remove a and b from the sensitivity list

B. No change needed; sensitivity list stays the same

C. Add enable to the sensitivity list

D. Replace sensitivity list with only enable

Solution

1. Step 1: Identify all signals affecting outputs

   Now enable controls output c along with a and b.

2. Step 2: Update sensitivity list accordingly

   To simulate correctly, enable must be added to the sensitivity list with a and b.

3. Final Answer:

   Add enable to the sensitivity list -> Option C

4. Quick Check:

   All input signals in sensitivity list = correct simulation [OK]

Hint: Add all signals that affect outputs to sensitivity list [OK]

Common Mistakes:

• Forgetting to add new control signals to sensitivity list
• Removing original signals from sensitivity list incorrectly
• Assuming sensitivity list auto-updates with code changes