Process sensitivity list in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this VHDL process?

Consider the following VHDL process. What will be the value of y after a changes from '0' to '1'?

VHDL

process(a, b)
begin
  if a = '1' then
    y <= '1';
  else
    y <= '0';
  end if;
end process;

A y becomes '1' only if b is also '1'

B y remains unchanged because b did not change

C y becomes '0' immediately after a changes to '1'

D y becomes '1' immediately after a changes to '1'

💡 Hint

Remember the process sensitivity list triggers the process when any signal in it changes.

The process sensitivity list includes a and b. When a changes, the process runs and sets y to '1' if a is '1'.

❓ Predict Output

intermediate

What happens if a signal is missing from the sensitivity list?

Given this process, what will happen if b changes from '0' to '1'?

VHDL

process(a)
begin
  y <= a and b;
end process;

A y does not update because b is not in the sensitivity list

B y updates only when a changes

C The code will not compile due to missing b in sensitivity list

D y updates immediately to reflect the new value of b

💡 Hint

Think about what triggers the process to run.

The process sensitivity list only includes a. Changes to b do not trigger the process, so y does not update immediately.

🔧 Debug

advanced

Identify the error caused by an incomplete sensitivity list

Analyze the following VHDL process. What problem will occur during simulation?

VHDL

process(clk, reset)
begin
  if reset = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

A The process will trigger too often causing simulation slowdown

B The process will cause a syntax error due to missing signals

C The process will update q correctly on every clock edge

D The process will not trigger on changes to d, causing q to not update correctly

💡 Hint

Consider which signals cause the process to run and which signals are read inside.

The process sensitivity list includes clk and reset, which is correct for this sequential D flip-flop with asynchronous reset. The signal d does not need to be included because it is sampled only on clock edges. The process triggers correctly and updates q as expected.

🧠 Conceptual

advanced

Why is it important to include all read signals in the sensitivity list?

Which statement best explains why all signals read inside a process must be in its sensitivity list?

A To reduce the number of times the process runs and improve performance

B To ensure the process triggers whenever any input changes, keeping outputs updated

C Because VHDL requires sensitivity lists to be empty for combinational logic

D To avoid syntax errors during compilation

💡 Hint

Think about how the process knows when to run.

Including all read signals in the sensitivity list ensures the process runs whenever any input changes, so outputs reflect the current inputs.

🚀 Application

expert

Determine the number of times the process triggers

Given the following process and signal changes, how many times will the process run?

process(a, b, c)
begin
  x <= a or b and c;
end process;

-- Signal changes in order:
a changes once
b changes twice
c changes once

A 4 times

B 3 times

C 1 time

D 2 times

💡 Hint

Count how many times any signal in the sensitivity list changes.

The process triggers once for each change in any signal in the sensitivity list. Here, a changes once, b twice, and c once, totaling 4 triggers.

Practice

1. What does the sensitivity list in a VHDL process specify?

easy

A. Which signals trigger the process to run when they change

B. The order in which signals are assigned values

C. The data types of signals inside the process

D. The clock frequency for the process execution

Solution

1. Step 1: Understand the role of sensitivity list

   The sensitivity list tells VHDL which signals to watch for changes.

2. Step 2: Identify what triggers the process

   The process runs only when a signal in the sensitivity list changes value.

3. Final Answer:

   Which signals trigger the process to run when they change -> Option A

4. Quick Check:

   Sensitivity list = triggers process run [OK]

Hint: Sensitivity list = signals that start the process [OK]

Common Mistakes:

• Thinking sensitivity list sets signal data types
• Confusing sensitivity list with signal assignment order
• Assuming sensitivity list controls clock frequency

2. Which of the following is the correct syntax for a process sensitivity list in VHDL?

easy

A. process {clk, reset}

B. process clk, reset

C. process [clk, reset]

D. process(clk, reset)

Solution

1. Step 1: Recall VHDL process syntax

   The sensitivity list is enclosed in parentheses after the keyword process.

2. Step 2: Match correct syntax

   Only the syntax with parentheses and comma-separated signals is correct: process(clk, reset)

3. Final Answer:

   process(clk, reset) -> Option D

4. Quick Check:

   Parentheses and commas = correct syntax [OK]

Hint: Use parentheses with commas for sensitivity list [OK]

Common Mistakes:

• Omitting parentheses around sensitivity list
• Using square or curly brackets instead of parentheses
• Separating signals with spaces instead of commas

3. Consider this VHDL process:

process(a, b)
begin
  c <= a and b;
end process;

What happens if signal b changes value?

medium

A. The process does not run because only a triggers it

B. The process runs and updates c

C. The process runs but c remains unchanged

D. The process causes a syntax error

Solution

1. Step 1: Check sensitivity list signals

   The process sensitivity list includes signals a and b.

2. Step 2: Understand process triggering

   When b changes, the process runs and updates c with a and b.

3. Final Answer:

   The process runs and updates c -> Option B

4. Quick Check:

   Signal in sensitivity list changed = process runs [OK]

Hint: Process runs when any sensitivity signal changes [OK]

Common Mistakes:

• Thinking only first signal triggers process
• Assuming process runs but output doesn't update
• Confusing syntax error with normal behavior

4. Identify the error in this VHDL process:

process(clk)
begin
  if reset = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

Assuming reset is a signal, what is the problem?

medium

A. Reset signal is missing from the sensitivity list

B. Clock signal should not be in the sensitivity list

C. The process should use falling_edge instead of rising_edge

D. The process syntax is correct with no errors

Solution

1. Step 1: Check signals used inside process

   The process uses reset and clk signals.

2. Step 2: Verify sensitivity list completeness

   Only clk is in the sensitivity list; reset is missing, which can cause simulation mismatches.

3. Final Answer:

   Reset signal is missing from the sensitivity list -> Option A

4. Quick Check:

   All input signals must be in sensitivity list [OK]

Hint: Include all input signals in sensitivity list [OK]

Common Mistakes:

• Ignoring signals that affect outputs in sensitivity list
• Thinking clock should be removed from sensitivity list
• Confusing edge detection with sensitivity list content

5. You have a process sensitive to signals a and b. Inside, you compute c <= a or b;. Later, you add a new signal enable that gates the output: if enable = '1' then c <= a or b; else c <= '0'; end if;
What must you do to the sensitivity list to ensure correct simulation?

hard

A. Remove a and b from the sensitivity list

B. No change needed; sensitivity list stays the same

C. Add enable to the sensitivity list

D. Replace sensitivity list with only enable

Solution

1. Step 1: Identify all signals affecting outputs

   Now enable controls output c along with a and b.

2. Step 2: Update sensitivity list accordingly

   To simulate correctly, enable must be added to the sensitivity list with a and b.

3. Final Answer:

   Add enable to the sensitivity list -> Option C

4. Quick Check:

   All input signals in sensitivity list = correct simulation [OK]

Hint: Add all signals that affect outputs to sensitivity list [OK]

Common Mistakes:

• Forgetting to add new control signals to sensitivity list
• Removing original signals from sensitivity list incorrectly
• Assuming sensitivity list auto-updates with code changes