Moore machine implementation in VHDL - Step-by-Step Execution

Concept Flow - Moore machine implementation

Start

↓

Reset State

↓

Wait for Clock

↓

Check Input

↓

Update State

↓

Output depends on State

↓

Repeat on next Clock

The Moore machine waits for a clock signal, updates its state based on input, and outputs depend only on the current state.

Execution Sample

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity moore_fsm is
  port(clk, reset, x: in std_logic;
       z: out std_logic);
end moore_fsm;

This code defines a Moore machine entity with clock, reset, input x, and output z.

Execution Table

Step	Clock	Reset	Input x	Current State	Next State	Output z	Action
1	0	1	0	S0	S0	0	Reset active, state set to S0, output 0
2	1	0	0	S0	S1	0	Clock rising edge, input 0, move to S1
3	0	0	0	S1	S1	1	No clock edge, state stays S1, output 1
4	1	0	1	S1	S2	1	Clock rising edge, input 1, move to S2
5	0	0	1	S2	S2	0	No clock edge, state stays S2, output 0
6	1	0	0	S2	S0	0	Clock rising edge, input 0, move to S0
7	0	0	0	S0	S0	0	No clock edge, state stays S0, output 0
8	1	1	0	S0	S0	0	Reset active again, state set to S0, output 0

💡 Simulation ends after reset reactivated at step 8.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	After 8
Current State	S0	S0	S1	S1	S2	S2	S0	S0	S0
Output z	0	0	0	1	1	0	0	0	0

Key Moments - 3 Insights

Why does the output depend only on the current state and not on the input?

In a Moore machine, output is generated from the current state only, as shown in the execution_table where output z changes only when the state changes, not directly on input.

What happens when reset is active during a clock cycle?

When reset is active (step 1 and 8), the state immediately goes to S0 and output is set accordingly, overriding normal state transitions.

Why does the state not change when clock is 0?

State updates happen only on the rising edge of the clock (clock=1), so when clock=0, the state and output remain stable as seen in steps 3, 5, and 7.

Visual Quiz - 3 Questions

Look at the execution_table, what is the output z at step 4?

A 1

B 0

C Undefined

D Same as input x

💡 Hint

Check the Output z column at step 4 in the execution_table.

At which step does the state first change from S0 to S1?

A Step 1

B Step 3

C Step 2

D Step 4

💡 Hint

Look at the Current State and Next State columns in the execution_table.

If reset is active at step 5, what would be the next state?

A S1

B S0

C S2

D No change

💡 Hint

Refer to steps 1 and 8 where reset forces state to S0.

Concept Snapshot

Moore Machine in VHDL:
- Output depends only on current state.
- State updates on clock rising edge.
- Reset sets state to initial.
- Inputs affect next state, not output directly.
- Use process blocks for state and output logic.

Full Transcript

This visual execution traces a Moore machine implemented in VHDL. The machine starts at state S0 with output 0. On each rising clock edge, it reads input x and updates its state accordingly. The output depends only on the current state, not directly on input. Reset forces the machine back to state S0 and output 0 immediately. The execution table shows step-by-step clock, reset, input, current and next states, output, and actions. Variable tracker shows how state and output change over time. Key moments clarify why output depends only on state, how reset affects state, and why state changes only on clock edges. The quiz tests understanding of output values, state transitions, and reset behavior. The snapshot summarizes the Moore machine's key rules and VHDL implementation style.

Practice

1. What is a key characteristic of a Moore machine in VHDL?

easy

A. Output depends only on the current state

B. Output depends on current state and input

C. Output changes asynchronously with input

D. Output depends only on input signals

Solution

1. Step 1: Understand Moore machine output behavior

   Moore machine outputs depend solely on the current state, not on inputs directly.

2. Step 2: Compare options with Moore machine definition

   Only 'Output depends only on the current state' matches Moore machine behavior.

3. Final Answer:

   Output depends only on the current state -> Option A

4. Quick Check:

   Moore output = current state only [OK]

Hint: Remember: Moore output ignores inputs directly [OK]

Common Mistakes:

• Confusing Moore with Mealy machine output
• Thinking output changes immediately with input
• Assuming output depends on input signals

2. Which VHDL process is typically used to update the current state in a Moore machine?

easy

A. Process sensitive only to output signals

B. Combinational process with sensitivity to inputs

C. Clocked process triggered on rising edge of clock

D. Asynchronous reset process without clock

Solution

1. Step 1: Identify state update mechanism in Moore machine

   The current state updates synchronously on clock edges, typically rising edge.

2. Step 2: Match process type to state update

   Only a clocked process triggered on rising clock edge updates state correctly.

3. Final Answer:

   Clocked process triggered on rising edge of clock -> Option C

4. Quick Check:

   State update = clocked process [OK]

Hint: State changes on clock edge, not input change [OK]

Common Mistakes:

• Using combinational process for state update
• Ignoring clock in state transition
• Confusing output process with state update

3. Given this VHDL snippet for a Moore machine output process:

process(current_state)
begin
  case current_state is
    when S0 => output_signal <= '0';
    when S1 => output_signal <= '1';
    when others => output_signal <= '0';
  end case;
end process;

What is the output when current_state = S1?

medium

A. '0'

B. '1'

C. 'Z' (high impedance)

D. No output assigned

Solution

1. Step 1: Analyze the case statement for current_state = S1

   When current_state is S1, output_signal is assigned '1'.

2. Step 2: Confirm output assignment

   The process explicitly sets output_signal to '1' for S1 state.

3. Final Answer:

   '1' -> Option B

4. Quick Check:

   State S1 output = '1' [OK]

Hint: Check case for current state to find output [OK]

Common Mistakes:

• Assuming output is '0' for all states
• Confusing 'others' case with S1
• Missing output assignment in process

4. Identify the error in this Moore machine state transition process:

process(clk)
begin
  if clk = '1' then
    current_state <= next_state;
  end if;
end process;

medium

A. Missing edge detection on clock signal

B. Incorrect use of non-blocking assignment

C. No reset signal included

D. Process sensitivity list is empty

Solution

1. Step 1: Check clock condition in process

   The process checks if clk = '1' but does not detect clock edge (rising_edge(clk)).

2. Step 2: Understand importance of edge detection

   Without edge detection, state updates continuously when clk is high, causing incorrect behavior.

3. Final Answer:

   Missing edge detection on clock signal -> Option A

4. Quick Check:

   Use rising_edge(clk) for proper clock sync [OK]

Hint: Use rising_edge(clk) for clocked processes [OK]

Common Mistakes:

• Using clk = '1' instead of rising_edge(clk)
• Ignoring reset signal importance
• Leaving sensitivity list empty

5. You want to design a Moore machine in VHDL that outputs '1' only after the input sequence '101' is detected. Which approach correctly implements the output logic?

hard

A. Output assigned asynchronously outside any process

B. Output assigned directly from input signals combinationally

C. Output assigned in next state logic process based on inputs

D. Output assigned in state process based only on current state

Solution

1. Step 1: Recall Moore machine output rule

   Moore machine output depends only on current state, not inputs directly.

2. Step 2: Determine correct output assignment

   Output must be assigned in a process sensitive to current state, not inputs or next state logic.

3. Final Answer:

   Output assigned in state process based only on current state -> Option D

4. Quick Check:

   Moore output = function of current state only [OK]

Hint: Assign output only from current state process [OK]

Common Mistakes:

• Assigning output from inputs directly
• Using next state logic for output
• Assigning output asynchronously