Moore machine implementation in VHDL - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a Moore machine in digital design?

A Moore machine is a finite state machine where the outputs depend only on the current state, not on the inputs.

beginner

In VHDL, how do you represent states for a Moore machine?

States are usually represented using an enumerated type, listing all possible states as named values.

intermediate

Why does a Moore machine output depend only on the state and not on inputs?

Because outputs are assigned based on the current state only, making output changes synchronous with state changes.

intermediate

What are the main parts of a Moore machine VHDL implementation?

1. State type declaration, 2. State register process (clocked), 3. Next state logic process, 4. Output logic based on current state.

beginner

How do you update the state in a Moore machine VHDL code?

You update the state inside a clocked process triggered on the rising edge of the clock, assigning the next state to the current state register.

In a Moore machine, the output depends on:

A Both current state and input

B Only the current input

C Only the current state

D Previous input

Moore machine outputs depend only on the current state, not on inputs.

Which VHDL construct is best to define the states of a Moore machine?

A Enumerated type

B Integer variable

C Boolean signal

D Array

States are best defined as an enumerated type for clarity and readability.

Where is the next state logic usually implemented in a Moore machine VHDL code?

A In the reset logic

B In a clocked process

C In the output assignment

D In a combinational process

Next state logic is combinational, deciding next state based on current state and inputs.

How are outputs assigned in a Moore machine VHDL implementation?

A Based on the current state only

B Based on inputs only

C Based on next state

D Based on previous output

Outputs depend only on the current state in a Moore machine.

What triggers the state update in a Moore machine VHDL code?

A Change in input signals

B Rising edge of the clock

C Falling edge of the clock

D Reset signal only

State updates happen on the rising edge of the clock in synchronous designs.

Explain the structure of a Moore machine VHDL implementation and how outputs are generated.

Think about separating state update and output logic.

Describe why Moore machines are useful and how their output behavior differs from Mealy machines.

Focus on output timing and dependency.

Practice

1. What is a key characteristic of a Moore machine in VHDL?

easy

A. Output depends only on the current state

B. Output depends on current state and input

C. Output changes asynchronously with input

D. Output depends only on input signals

Solution

1. Step 1: Understand Moore machine output behavior

   Moore machine outputs depend solely on the current state, not on inputs directly.

2. Step 2: Compare options with Moore machine definition

   Only 'Output depends only on the current state' matches Moore machine behavior.

3. Final Answer:

   Output depends only on the current state -> Option A

4. Quick Check:

   Moore output = current state only [OK]

Hint: Remember: Moore output ignores inputs directly [OK]

Common Mistakes:

• Confusing Moore with Mealy machine output
• Thinking output changes immediately with input
• Assuming output depends on input signals

2. Which VHDL process is typically used to update the current state in a Moore machine?

easy

A. Process sensitive only to output signals

B. Combinational process with sensitivity to inputs

C. Clocked process triggered on rising edge of clock

D. Asynchronous reset process without clock

Solution

1. Step 1: Identify state update mechanism in Moore machine

   The current state updates synchronously on clock edges, typically rising edge.

2. Step 2: Match process type to state update

   Only a clocked process triggered on rising clock edge updates state correctly.

3. Final Answer:

   Clocked process triggered on rising edge of clock -> Option C

4. Quick Check:

   State update = clocked process [OK]

Hint: State changes on clock edge, not input change [OK]

Common Mistakes:

• Using combinational process for state update
• Ignoring clock in state transition
• Confusing output process with state update

3. Given this VHDL snippet for a Moore machine output process:

process(current_state)
begin
  case current_state is
    when S0 => output_signal <= '0';
    when S1 => output_signal <= '1';
    when others => output_signal <= '0';
  end case;
end process;

What is the output when current_state = S1?

medium

A. '0'

B. '1'

C. 'Z' (high impedance)

D. No output assigned

Solution

1. Step 1: Analyze the case statement for current_state = S1

   When current_state is S1, output_signal is assigned '1'.

2. Step 2: Confirm output assignment

   The process explicitly sets output_signal to '1' for S1 state.

3. Final Answer:

   '1' -> Option B

4. Quick Check:

   State S1 output = '1' [OK]

Hint: Check case for current state to find output [OK]

Common Mistakes:

• Assuming output is '0' for all states
• Confusing 'others' case with S1
• Missing output assignment in process

4. Identify the error in this Moore machine state transition process:

process(clk)
begin
  if clk = '1' then
    current_state <= next_state;
  end if;
end process;

medium

A. Missing edge detection on clock signal

B. Incorrect use of non-blocking assignment

C. No reset signal included

D. Process sensitivity list is empty

Solution

1. Step 1: Check clock condition in process

   The process checks if clk = '1' but does not detect clock edge (rising_edge(clk)).

2. Step 2: Understand importance of edge detection

   Without edge detection, state updates continuously when clk is high, causing incorrect behavior.

3. Final Answer:

   Missing edge detection on clock signal -> Option A

4. Quick Check:

   Use rising_edge(clk) for proper clock sync [OK]

Hint: Use rising_edge(clk) for clocked processes [OK]

Common Mistakes:

• Using clk = '1' instead of rising_edge(clk)
• Ignoring reset signal importance
• Leaving sensitivity list empty

5. You want to design a Moore machine in VHDL that outputs '1' only after the input sequence '101' is detected. Which approach correctly implements the output logic?

hard

A. Output assigned asynchronously outside any process

B. Output assigned directly from input signals combinationally

C. Output assigned in next state logic process based on inputs

D. Output assigned in state process based only on current state

Solution

1. Step 1: Recall Moore machine output rule

   Moore machine output depends only on current state, not inputs directly.

2. Step 2: Determine correct output assignment

   Output must be assigned in a process sensitive to current state, not inputs or next state logic.

3. Final Answer:

   Output assigned in state process based only on current state -> Option D

4. Quick Check:

   Moore output = function of current state only [OK]

Hint: Assign output only from current state process [OK]

Common Mistakes:

• Assigning output from inputs directly
• Using next state logic for output
• Assigning output asynchronously