Moore machine implementation in VHDL - Mini Project: Build & Apply

Moore Machine Implementation in VHDL

📖 Scenario: You are designing a simple Moore state machine in VHDL to control a traffic light system. The machine has three states: Red, Green, and Yellow. Each state outputs a signal to turn on the corresponding light.

🎯 Goal: Build a Moore machine in VHDL with three states and outputs that represent the traffic light signals. The machine should cycle through the states in order: Red → Green → Yellow → Red, and so on.

📋 What You'll Learn

Create a VHDL entity and architecture for the Moore machine

Define a type for the states: Red, Green, Yellow

Create a signal to hold the current state

Use a clock input to trigger state transitions

Output signals for Red, Green, and Yellow lights

Cycle through states in the order Red → Green → Yellow → Red

💡 Why This Matters

🌍 Real World

Traffic light controllers use Moore machines to ensure stable outputs based on states, making this a practical example of hardware design.

💼 Career

Understanding Moore machines and VHDL is essential for FPGA and ASIC design engineers working on digital control systems.

1

Define the VHDL entity and state type

Write the VHDL entity named TrafficLight with inputs clk and reset (both std_logic). Inside the architecture, define a type called state_type with states Red, Green, and Yellow. Also declare a signal current_state of type state_type.

VHDL

-- Your code here

Hint

Start by declaring the entity with inputs and outputs. Then define the states as a type and create a signal to hold the current state.

2

Add state transition logic with clock and reset

Inside the architecture, add a process sensitive to clk and reset. On reset (when reset = '1'), set current_state to Red. On the rising edge of clk, update current_state to the next state in the sequence: Red → Green, Green → Yellow, Yellow → Red.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TrafficLight is
    Port (
        clk : in std_logic;
        reset : in std_logic;
        red_light : out std_logic;
        green_light : out std_logic;
        yellow_light : out std_logic
    );
end TrafficLight;

architecture Behavioral of TrafficLight is
    type state_type is (Red, Green, Yellow);
    signal current_state : state_type := Red;
begin
    -- Add process for state transitions here
end Behavioral;

Hint

Use a process triggered by clock and reset. On reset, set state to Red. On clock rising edge, use a case statement to move to the next state.

3

Add output logic for the lights based on current state

Add a combinational process or concurrent assignments to set the outputs red_light, green_light, and yellow_light to '1' when the current_state matches their color, and '0' otherwise.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TrafficLight is
    Port (
        clk : in std_logic;
        reset : in std_logic;
        red_light : out std_logic;
        green_light : out std_logic;
        yellow_light : out std_logic
    );
end TrafficLight;

architecture Behavioral of TrafficLight is
    type state_type is (Red, Green, Yellow);
    signal current_state : state_type := Red;
begin
    process(clk, reset)
    begin
        if reset = '1' then
            current_state 
                    current_state 
                    current_state 
                    current_state <= Red;
            end case;
        end if;
    end process;

    -- Your code here
end Behavioral;

Hint

Use conditional signal assignments to set each light output to '1' only when the current state matches its color.

4

Test the Moore machine output

Write a simple testbench process inside the architecture that applies a reset pulse and then clocks the machine through several cycles. Print the values of red_light, green_light, and yellow_light after each clock to verify the outputs cycle correctly.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TrafficLight is
    Port (
        clk : in std_logic;
        reset : in std_logic;
        red_light : out std_logic;
        green_light : out std_logic;
        yellow_light : out std_logic
    );
end TrafficLight;

architecture Behavioral of TrafficLight is
    type state_type is (Red, Green, Yellow);
    signal current_state : state_type := Red;

    signal clk_tb : std_logic := '0';
    signal reset_tb : std_logic := '0';

begin
    process(clk, reset)
    begin
        if reset = '1' then
            current_state 
                    current_state 
                    current_state 
                    current_state <= Red;
            end case;
        end if;
    end process;

    red_light <= '1' when current_state = Red else '0';
    green_light <= '1' when current_state = Green else '0';
    yellow_light <= '1' when current_state = Yellow else '0';

    -- Your testbench process here
end Behavioral;

Hint

Create a test process that toggles a test clock and reset signal. Use textio to print the output signals after each clock cycle.

Practice

1. What is a key characteristic of a Moore machine in VHDL?

easy

A. Output depends only on the current state

B. Output depends on current state and input

C. Output changes asynchronously with input

D. Output depends only on input signals

Solution

1. Step 1: Understand Moore machine output behavior

   Moore machine outputs depend solely on the current state, not on inputs directly.

2. Step 2: Compare options with Moore machine definition

   Only 'Output depends only on the current state' matches Moore machine behavior.

3. Final Answer:

   Output depends only on the current state -> Option A

4. Quick Check:

   Moore output = current state only [OK]

Hint: Remember: Moore output ignores inputs directly [OK]

Common Mistakes:

• Confusing Moore with Mealy machine output
• Thinking output changes immediately with input
• Assuming output depends on input signals

2. Which VHDL process is typically used to update the current state in a Moore machine?

easy

A. Process sensitive only to output signals

B. Combinational process with sensitivity to inputs

C. Clocked process triggered on rising edge of clock

D. Asynchronous reset process without clock

Solution

1. Step 1: Identify state update mechanism in Moore machine

   The current state updates synchronously on clock edges, typically rising edge.

2. Step 2: Match process type to state update

   Only a clocked process triggered on rising clock edge updates state correctly.

3. Final Answer:

   Clocked process triggered on rising edge of clock -> Option C

4. Quick Check:

   State update = clocked process [OK]

Hint: State changes on clock edge, not input change [OK]

Common Mistakes:

• Using combinational process for state update
• Ignoring clock in state transition
• Confusing output process with state update

3. Given this VHDL snippet for a Moore machine output process:

process(current_state)
begin
  case current_state is
    when S0 => output_signal <= '0';
    when S1 => output_signal <= '1';
    when others => output_signal <= '0';
  end case;
end process;

What is the output when current_state = S1?

medium

A. '0'

B. '1'

C. 'Z' (high impedance)

D. No output assigned

Solution

1. Step 1: Analyze the case statement for current_state = S1

   When current_state is S1, output_signal is assigned '1'.

2. Step 2: Confirm output assignment

   The process explicitly sets output_signal to '1' for S1 state.

3. Final Answer:

   '1' -> Option B

4. Quick Check:

   State S1 output = '1' [OK]

Hint: Check case for current state to find output [OK]

Common Mistakes:

• Assuming output is '0' for all states
• Confusing 'others' case with S1
• Missing output assignment in process

4. Identify the error in this Moore machine state transition process:

process(clk)
begin
  if clk = '1' then
    current_state <= next_state;
  end if;
end process;

medium

A. Missing edge detection on clock signal

B. Incorrect use of non-blocking assignment

C. No reset signal included

D. Process sensitivity list is empty

Solution

1. Step 1: Check clock condition in process

   The process checks if clk = '1' but does not detect clock edge (rising_edge(clk)).

2. Step 2: Understand importance of edge detection

   Without edge detection, state updates continuously when clk is high, causing incorrect behavior.

3. Final Answer:

   Missing edge detection on clock signal -> Option A

4. Quick Check:

   Use rising_edge(clk) for proper clock sync [OK]

Hint: Use rising_edge(clk) for clocked processes [OK]

Common Mistakes:

• Using clk = '1' instead of rising_edge(clk)
• Ignoring reset signal importance
• Leaving sensitivity list empty

5. You want to design a Moore machine in VHDL that outputs '1' only after the input sequence '101' is detected. Which approach correctly implements the output logic?

hard

A. Output assigned asynchronously outside any process

B. Output assigned directly from input signals combinationally

C. Output assigned in next state logic process based on inputs

D. Output assigned in state process based only on current state

Solution

1. Step 1: Recall Moore machine output rule

   Moore machine output depends only on current state, not inputs directly.

2. Step 2: Determine correct output assignment

   Output must be assigned in a process sensitive to current state, not inputs or next state logic.

3. Final Answer:

   Output assigned in state process based only on current state -> Option D

4. Quick Check:

   Moore output = function of current state only [OK]

Hint: Assign output only from current state process [OK]

Common Mistakes:

• Assigning output from inputs directly
• Using next state logic for output
• Assigning output asynchronously