Moore machine implementation in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the state type in a Moore machine.

VHDL

type state_type is ([1]);

Drag options to blanks, or click blank then click option'

AIDLE, PROCESS, DONE

BIDLE_PROCESS_DONE

Cstate1 state2 state3

D1, 2, 3

Attempts:

3 left

💡 Hint

Common Mistakes

Writing states as a single string without commas.

Using numbers instead of state names.

Separating states with spaces instead of commas.

States in VHDL are declared as an enumerated type listing each state separated by commas.

2fill in blank

medium

Complete the code to define the state register signal.

VHDL

signal current_state : [1] := IDLE;

Drag options to blanks, or click blank then click option'

Ainteger

Bstd_logic

Cbit

Dstate_type

Attempts:

3 left

💡 Hint

Common Mistakes

Using std_logic or bit instead of the state_type.

Using integer which is not suitable for enumerated states.

The state register must be of the state_type defined for the states.

3fill in blank

hard

Fix the error in the process sensitivity list for the Moore machine.

VHDL

process([1])
begin
  if rising_edge(clk) then
    -- state transitions
  end if;
end process;

Drag options to blanks, or click blank then click option'

Aclk

Brst

Cclk, rst

Dclk or rst

Attempts:

3 left

💡 Hint

Common Mistakes

Including reset in the sensitivity list causing asynchronous behavior.

Using 'or' keyword which is not valid in VHDL sensitivity lists.

The process should be sensitive only to the clock signal for synchronous state transitions.

4fill in blank

hard

Fill both blanks to complete the output logic of the Moore machine.

VHDL

with current_state select
  output_signal <= [1] when IDLE,
                   [2] when PROCESS,
                   '0' when others;

Drag options to blanks, or click blank then click option'

A'0'

B'1'

C'Z'

D'X'

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning outputs based on inputs instead of states.

Using undefined output values like 'Z' or 'X' incorrectly.

Outputs depend only on the current state in a Moore machine. Here, output is '0' in IDLE and '1' in PROCESS.

5fill in blank

hard

Fill all three blanks to complete the state transition logic inside the clocked process.

VHDL

process(clk)
begin
  if rising_edge(clk) then
    if rst = '1' then
      current_state <= [1];
    else
      case current_state is
        when IDLE =>
          if start = '1' then
            current_state <= [2];
          else
            current_state <= IDLE;
          end if;
        when PROCESS =>
          if done = '1' then
            current_state <= [3];
          else
            current_state <= PROCESS;
          end if;
        when others =>
          current_state <= IDLE;
      end case;
    end if;
  end if;
end process;

Drag options to blanks, or click blank then click option'

AIDLE

BPROCESS

CDONE

DSTART

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning wrong states on reset or transitions.

Using undefined states like START.

On reset, state goes to IDLE. From IDLE, if start is '1', go to PROCESS. From PROCESS, if done is '1', go to DONE.

Practice

1. What is a key characteristic of a Moore machine in VHDL?

easy

A. Output depends only on the current state

B. Output depends on current state and input

C. Output changes asynchronously with input

D. Output depends only on input signals

Solution

1. Step 1: Understand Moore machine output behavior

   Moore machine outputs depend solely on the current state, not on inputs directly.

2. Step 2: Compare options with Moore machine definition

   Only 'Output depends only on the current state' matches Moore machine behavior.

3. Final Answer:

   Output depends only on the current state -> Option A

4. Quick Check:

   Moore output = current state only [OK]

Hint: Remember: Moore output ignores inputs directly [OK]

Common Mistakes:

• Confusing Moore with Mealy machine output
• Thinking output changes immediately with input
• Assuming output depends on input signals

2. Which VHDL process is typically used to update the current state in a Moore machine?

easy

A. Process sensitive only to output signals

B. Combinational process with sensitivity to inputs

C. Clocked process triggered on rising edge of clock

D. Asynchronous reset process without clock

Solution

1. Step 1: Identify state update mechanism in Moore machine

   The current state updates synchronously on clock edges, typically rising edge.

2. Step 2: Match process type to state update

   Only a clocked process triggered on rising clock edge updates state correctly.

3. Final Answer:

   Clocked process triggered on rising edge of clock -> Option C

4. Quick Check:

   State update = clocked process [OK]

Hint: State changes on clock edge, not input change [OK]

Common Mistakes:

• Using combinational process for state update
• Ignoring clock in state transition
• Confusing output process with state update

3. Given this VHDL snippet for a Moore machine output process:

process(current_state)
begin
  case current_state is
    when S0 => output_signal <= '0';
    when S1 => output_signal <= '1';
    when others => output_signal <= '0';
  end case;
end process;

What is the output when current_state = S1?

medium

A. '0'

B. '1'

C. 'Z' (high impedance)

D. No output assigned

Solution

1. Step 1: Analyze the case statement for current_state = S1

   When current_state is S1, output_signal is assigned '1'.

2. Step 2: Confirm output assignment

   The process explicitly sets output_signal to '1' for S1 state.

3. Final Answer:

   '1' -> Option B

4. Quick Check:

   State S1 output = '1' [OK]

Hint: Check case for current state to find output [OK]

Common Mistakes:

• Assuming output is '0' for all states
• Confusing 'others' case with S1
• Missing output assignment in process

4. Identify the error in this Moore machine state transition process:

process(clk)
begin
  if clk = '1' then
    current_state <= next_state;
  end if;
end process;

medium

A. Missing edge detection on clock signal

B. Incorrect use of non-blocking assignment

C. No reset signal included

D. Process sensitivity list is empty

Solution

1. Step 1: Check clock condition in process

   The process checks if clk = '1' but does not detect clock edge (rising_edge(clk)).

2. Step 2: Understand importance of edge detection

   Without edge detection, state updates continuously when clk is high, causing incorrect behavior.

3. Final Answer:

   Missing edge detection on clock signal -> Option A

4. Quick Check:

   Use rising_edge(clk) for proper clock sync [OK]

Hint: Use rising_edge(clk) for clocked processes [OK]

Common Mistakes:

• Using clk = '1' instead of rising_edge(clk)
• Ignoring reset signal importance
• Leaving sensitivity list empty

5. You want to design a Moore machine in VHDL that outputs '1' only after the input sequence '101' is detected. Which approach correctly implements the output logic?

hard

A. Output assigned asynchronously outside any process

B. Output assigned directly from input signals combinationally

C. Output assigned in next state logic process based on inputs

D. Output assigned in state process based only on current state

Solution

1. Step 1: Recall Moore machine output rule

   Moore machine output depends only on current state, not inputs directly.

2. Step 2: Determine correct output assignment

   Output must be assigned in a process sensitive to current state, not inputs or next state logic.

3. Final Answer:

   Output assigned in state process based only on current state -> Option D

4. Quick Check:

   Moore output = function of current state only [OK]

Hint: Assign output only from current state process [OK]

Common Mistakes:

• Assigning output from inputs directly
• Using next state logic for output
• Assigning output asynchronously