Moore machine implementation in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple Moore machine VHDL code

What is the output on the signal y after the input sequence 101 is applied to this Moore machine?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity moore_simple is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           x : in STD_LOGIC;
           y : out STD_LOGIC);
end moore_simple;

architecture Behavioral of moore_simple is
    type state_type is (S0, S1);
    signal state, next_state : state_type;
begin
    process(clk, rst)
    begin
        if rst = '1' then
            state <= S0;
        elsif rising_edge(clk) then
            state <= next_state;
        end if;
    end process;

    process(state, x)
    begin
        case state is
            when S0 =>
                if x = '1' then
                    next_state <= S1;
                else
                    next_state <= S0;
                end if;
            when S1 =>
                if x = '1' then
                    next_state <= S0;
                else
                    next_state <= S1;
                end if;
        end case;
    end process;

    process(state)
    begin
        case state is
            when S0 => y <= '0';
            when S1 => y <= '1';
        end case;
    end process;
end Behavioral;

A y outputs sequence: 1, 0, 0

B y outputs sequence: 0, 0, 1

C y outputs sequence: 1, 1, 0

D y outputs sequence: 0, 1, 1

💡 Hint

Remember that Moore machine outputs depend only on the current state, not the input.

The machine starts in S0 with output 0. Input '1' moves it to S1 with output 1, and next input '0' keeps it in S1 because the transition only moves back to S0 if input is '1' from S1. So outputs are 0, 1, 1.

🧠 Conceptual

intermediate

Understanding Moore machine output timing

In a Moore machine implemented in VHDL, when does the output signal typically change relative to the clock?

A Output changes on the rising edge of the clock after state update

B Output changes on the falling edge of the clock

C Output changes immediately when input changes

D Output changes asynchronously without clock

💡 Hint

Think about when the state is updated and how output depends on state.

In Moore machines, output depends only on the current state. The state updates on the rising clock edge, so output changes after the state update on the clock edge.

🔧 Debug

advanced

Identify the error in this Moore machine VHDL code

What error will this VHDL code produce when synthesizing a Moore machine?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity moore_buggy is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           x : in STD_LOGIC;
           y : out STD_LOGIC);
end moore_buggy;

architecture Behavioral of moore_buggy is
    type state_type is (S0, S1);
    signal state, next_state : state_type;
begin
    process(clk, rst)
    begin
        if rst = '1' then
            state <= S0;
        elsif rising_edge(clk) then
            state <= next_state;
        end if;
    end process;

    process(state, x)
    begin
        case state is
            when S0 =>
                if x = '1' then
                    next_state <= S1;
                -- missing else branch here
                else
                    next_state <= S0;
                end if;
            when S1 =>
                if x = '0' then
                    next_state <= S0;
                else
                    next_state <= S1;
                end if;
        end case;
    end process;

    process(state)
    begin
        case state is
            when S0 => y <= '0';
            when S1 => y <= '1';
        end case;
    end process;
end Behavioral;

A No error, code synthesizes correctly

B Synthesis error due to incomplete if statement in state transition

C Output y will never change

D Runtime error due to uninitialized signal

💡 Hint

Check if all possible input conditions assign next_state in every branch.

In the process for next_state, the 'when S0' branch lacks an else clause, so next_state is not assigned for x='0'. This causes a latch inference or synthesis error.

📝 Syntax

advanced

Identify the syntax error in this Moore machine VHDL snippet

Which option correctly identifies the syntax error in this VHDL code snippet?

VHDL

process(state)
begin
    case state is
        when S0 => y <= '0';
        when S1 => y <= '1';
    end case;
end process;

A Missing semicolon after y <= '0' in when S0 branch

B Missing end process statement

C Incorrect case statement syntax

D Missing signal declaration for y

💡 Hint

Check each line for proper statement termination.

In VHDL, each assignment statement must end with a semicolon. The line 'y <= '0'' is missing a semicolon.

🚀 Application

expert

Number of states in a Moore machine for a given sequence detector

You want to design a Moore machine in VHDL that detects the sequence '1101' on input x. How many states are needed at minimum to implement this detector?

A 6 states

B 7 states

C 5 states

D 4 states

💡 Hint

Think about how many partial matches of the sequence you need to remember.

To detect '1101', the machine must remember progress through the sequence: no match, matched '1', matched '11', matched '110', and matched '1101'. This requires 5 states.

Practice

1. What is a key characteristic of a Moore machine in VHDL?

easy

A. Output depends only on the current state

B. Output depends on current state and input

C. Output changes asynchronously with input

D. Output depends only on input signals

Solution

1. Step 1: Understand Moore machine output behavior

   Moore machine outputs depend solely on the current state, not on inputs directly.

2. Step 2: Compare options with Moore machine definition

   Only 'Output depends only on the current state' matches Moore machine behavior.

3. Final Answer:

   Output depends only on the current state -> Option A

4. Quick Check:

   Moore output = current state only [OK]

Hint: Remember: Moore output ignores inputs directly [OK]

Common Mistakes:

• Confusing Moore with Mealy machine output
• Thinking output changes immediately with input
• Assuming output depends on input signals

2. Which VHDL process is typically used to update the current state in a Moore machine?

easy

A. Process sensitive only to output signals

B. Combinational process with sensitivity to inputs

C. Clocked process triggered on rising edge of clock

D. Asynchronous reset process without clock

Solution

1. Step 1: Identify state update mechanism in Moore machine

   The current state updates synchronously on clock edges, typically rising edge.

2. Step 2: Match process type to state update

   Only a clocked process triggered on rising clock edge updates state correctly.

3. Final Answer:

   Clocked process triggered on rising edge of clock -> Option C

4. Quick Check:

   State update = clocked process [OK]

Hint: State changes on clock edge, not input change [OK]

Common Mistakes:

• Using combinational process for state update
• Ignoring clock in state transition
• Confusing output process with state update

3. Given this VHDL snippet for a Moore machine output process:

process(current_state)
begin
  case current_state is
    when S0 => output_signal <= '0';
    when S1 => output_signal <= '1';
    when others => output_signal <= '0';
  end case;
end process;

What is the output when current_state = S1?

medium

A. '0'

B. '1'

C. 'Z' (high impedance)

D. No output assigned

Solution

1. Step 1: Analyze the case statement for current_state = S1

   When current_state is S1, output_signal is assigned '1'.

2. Step 2: Confirm output assignment

   The process explicitly sets output_signal to '1' for S1 state.

3. Final Answer:

   '1' -> Option B

4. Quick Check:

   State S1 output = '1' [OK]

Hint: Check case for current state to find output [OK]

Common Mistakes:

• Assuming output is '0' for all states
• Confusing 'others' case with S1
• Missing output assignment in process

4. Identify the error in this Moore machine state transition process:

process(clk)
begin
  if clk = '1' then
    current_state <= next_state;
  end if;
end process;

medium

A. Missing edge detection on clock signal

B. Incorrect use of non-blocking assignment

C. No reset signal included

D. Process sensitivity list is empty

Solution

1. Step 1: Check clock condition in process

   The process checks if clk = '1' but does not detect clock edge (rising_edge(clk)).

2. Step 2: Understand importance of edge detection

   Without edge detection, state updates continuously when clk is high, causing incorrect behavior.

3. Final Answer:

   Missing edge detection on clock signal -> Option A

4. Quick Check:

   Use rising_edge(clk) for proper clock sync [OK]

Hint: Use rising_edge(clk) for clocked processes [OK]

Common Mistakes:

• Using clk = '1' instead of rising_edge(clk)
• Ignoring reset signal importance
• Leaving sensitivity list empty

5. You want to design a Moore machine in VHDL that outputs '1' only after the input sequence '101' is detected. Which approach correctly implements the output logic?

hard

A. Output assigned asynchronously outside any process

B. Output assigned directly from input signals combinationally

C. Output assigned in next state logic process based on inputs

D. Output assigned in state process based only on current state

Solution

1. Step 1: Recall Moore machine output rule

   Moore machine output depends only on current state, not inputs directly.

2. Step 2: Determine correct output assignment

   Output must be assigned in a process sensitive to current state, not inputs or next state logic.

3. Final Answer:

   Output assigned in state process based only on current state -> Option D

4. Quick Check:

   Moore output = function of current state only [OK]

Hint: Assign output only from current state process [OK]

Common Mistakes:

• Assigning output from inputs directly
• Using next state logic for output
• Assigning output asynchronously