Case statement in process in VHDL - Step-by-Step Execution

Concept Flow - Case statement in process

Start process

↓

Evaluate case expression

↓

Match expression with case choices?

No→Execute 'when others'

Yes↓

Execute matched case branch

↓

End process

The process starts, evaluates the case expression, matches it to one of the choices, executes the matched branch or 'others' if no match, then ends.

Execution Sample

VHDL

process(sel)
begin
  case sel is
    when "00" => out <= '0';
    when "01" => out <= '1';
    when others => out <= 'Z';
  end case;
end process;

This process sets 'out' based on the 2-bit input 'sel' using a case statement.

Execution Table

Step	sel value	Case condition	Branch taken	Output (out)
1	"00"	sel = "00"	when "00"	'0'
2	"01"	sel = "01"	when "01"	'1'
3	"10"	sel = "10"	when others	'Z'
4	"11"	sel = "11"	when others	'Z'
5	N/A	No more inputs	Process ends	Output stable

💡 Process ends after all sel values tested; case matches or defaults to 'others'.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	Final
sel	N/A	"00"	"01"	"10"	"11"	N/A
out	U (undefined)	'0'	'1'	'Z'	'Z'	'Z'

Key Moments - 2 Insights

Why does the 'when others' branch execute for sel = "10" and "11"?

Because the case statement only explicitly matches "00" and "01", any other value like "10" or "11" falls to the 'when others' branch as shown in execution_table rows 3 and 4.

What happens if sel matches no explicit case and there is no 'when others'?

The process would be incomplete and may cause simulation errors or latches. The 'when others' ensures all cases are covered, as seen in the example.

Visual Quiz - 3 Questions

Look at the execution_table, what is the output 'out' when sel = "01"?

A '1'

B '0'

C 'Z'

D Undefined

💡 Hint

Check execution_table row 2 under 'Output (out)' for sel = "01".

At which step does the case statement use the 'when others' branch?

A Step 1

B Step 2

C Step 3

D Step 5

💡 Hint

Look at execution_table rows where 'Branch taken' is 'when others'.

If we add 'when "10" => out <= 'X';' to the case, what changes in the output for sel = "10"?

A Output becomes '1'

B Output becomes 'X' instead of 'Z'

C Output stays 'Z'

D Output becomes undefined

💡 Hint

Adding an explicit match changes the branch taken for that sel value, see variable_tracker for output changes.

Concept Snapshot

VHDL case statement in process:
- Syntax: case expression is when choice => statements; ... when others => statements; end case;
- Matches expression to choices, executes matching branch
- 'when others' covers all unmatched cases
- Used inside process for conditional assignments
- Ensures all cases handled to avoid latches

Full Transcript

This visual trace shows how a VHDL process uses a case statement to assign output based on a 2-bit input 'sel'. The process evaluates 'sel', matches it to defined cases "00" and "01", or defaults to 'when others' for other values. The output 'out' changes accordingly. The variable tracker shows 'sel' and 'out' values step-by-step. Key moments clarify why 'when others' is important and how missing it can cause issues. The quiz tests understanding of output values and case matching. This helps beginners see exactly how case statements control flow inside VHDL processes.

Practice

1. What is the main purpose of a case statement inside a VHDL process?

easy

A. To select actions based on the value of a signal

B. To declare new signals inside the process

C. To loop through a range of values

D. To assign default values to all signals

Solution

1. Step 1: Understand the role of case statement

   The case statement chooses different actions depending on the value of a signal.

2. Step 2: Compare with other options

   Declaring signals, looping, or assigning defaults are not the main purpose of case.

3. Final Answer:

   To select actions based on the value of a signal -> Option A

4. Quick Check:

   Case statement = select actions by signal value [OK]

Hint: Case picks actions by signal value inside process [OK]

Common Mistakes:

• Thinking case declares signals
• Confusing case with loops
• Assuming case assigns default values

2. Which of the following is the correct syntax to start a case statement inside a VHDL process for signal sel?

easy

A. switch sel is

B. case (sel) then

C. if sel then

D. case sel is

Solution

1. Step 1: Recall VHDL case syntax

   The correct syntax to start a case statement is case signal_name is.

2. Step 2: Check each option

   case sel is matches the correct syntax. Options A, B, and D are incorrect VHDL syntax.

3. Final Answer:

   case sel is -> Option D

4. Quick Check:

   Correct case syntax = "case signal is" [OK]

Hint: Use 'case signal is' to start a case statement [OK]

Common Mistakes:

• Using 'switch' instead of 'case'
• Adding parentheses or 'then' incorrectly
• Confusing case with if statement

3. Given the following VHDL process, what will be the value of out_signal when sel = "10"?

process(sel)
begin
  case sel is
    when "00" => out_signal <= '0';
    when "01" => out_signal <= '1';
    when "10" => out_signal <= '0';
    when others => out_signal <= '1';
  end case;
end process;

medium

A. '1'

B. Syntax error

C. '0'

D. Undefined

Solution

1. Step 1: Find matching case branch for sel = "10"

   The case statement has a branch when "10" => out_signal <= '0'; which matches the input.

2. Step 2: Determine assigned value

   For sel = "10", out_signal is assigned '0'.

3. Final Answer:

   '0' -> Option C

4. Quick Check:

   sel "10" sets out_signal to '0' [OK]

Hint: Match sel value to case branch to find output [OK]

Common Mistakes:

• Choosing default 'others' branch incorrectly
• Confusing '0' and '1' assignments
• Assuming syntax error without checking code

4. Identify the error in this VHDL process using a case statement:

process(sel)
begin
  case sel is
    when "00" => out_signal <= '0';
    when "01" => out_signal <= '1';
    when others => out_signal <= '0';
  end case;
end process;

medium

A. No error, code is correct

B. Missing semicolon after 'end case'

C. Missing 'when "10"' branch for sel

D. Incorrect use of 'others' keyword

Solution

1. Step 1: Check syntax and completeness

   The case statement covers "00", "01", and uses when others to cover all other values.

2. Step 2: Verify syntax correctness

   Semicolons and keywords are correctly placed; no syntax errors found.

3. Final Answer:

   No error, code is correct -> Option A

4. Quick Check:

   Proper use of 'others' covers missing cases [OK]

Hint: Use 'when others' to cover all missing cases [OK]

Common Mistakes:

• Thinking all cases must be listed explicitly
• Assuming missing branch causes error without 'others'
• Misplacing semicolons

5. You want to design a VHDL process that sets out_signal to '1' only when sel is "01" or "11", and '0' otherwise. Which case statement inside the process correctly implements this?

hard

A. case sel is
when "01" | "11" => out_signal <= '1';
when others => out_signal <= '0';
end case;

B. case sel is
when "01" => out_signal <= '1';
when "11" => out_signal <= '1';
when others => out_signal <= '0';
end case;

C. case sel is
when "01" => out_signal <= '1';
when others => out_signal <= '0';
end case;

D. case sel is
when "01" => out_signal <= '1';
when "10" => out_signal <= '1';
when others => out_signal <= '0';
end case;

Solution

1. Step 1: Identify required conditions

   Set out_signal to '1' only for sel = "01" or sel = "11", else '0'.

2. Step 2: Check each option for correctness

   case sel is when "01" | "11" => out_signal <= '1'; when others => out_signal <= '0'; end case; uses invalid syntax with '|' for multiple choices in VHDL case. case sel is when "01" => out_signal <= '1'; when "11" => out_signal <= '1'; when others => out_signal <= '0'; end case; lists both cases separately, which is correct. case sel is when "01" => out_signal <= '1'; when others => out_signal <= '0'; end case; misses "11" case. case sel is when "01" => out_signal <= '1'; when "10" => out_signal <= '1'; when others => out_signal <= '0'; end case; incorrectly uses "10" instead of "11".

3. Final Answer:

   Option B with separate when clauses for "01" and "11" -> Option B

4. Quick Check:

   Separate when lines for each value = correct VHDL [OK]

Hint: List each case separately; no '|' for multiple values in VHDL [OK]

Common Mistakes:

• Using '|' to combine cases (invalid in VHDL)
• Missing one required case
• Confusing similar bit patterns