Case statement in process in VHDL - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is the purpose of a case statement inside a VHDL process?

A case statement inside a VHDL process is used to select one of many possible actions based on the value of a signal or variable. It helps to write clear and organized conditional logic.

beginner

How do you start a case statement in VHDL inside a process?

You write case <expression> is where <expression> is the signal or variable you want to check. Then you list when options followed by actions, ending with end case;.

intermediate

What happens if none of the when choices in a case statement match the expression?

If no when choice matches, and there is a when others clause, that block runs. If when others is missing, it causes a compilation error because VHDL requires all cases to be covered.

intermediate

Can you use a case statement outside a process in VHDL?

No, the case statement must be inside a process or a subprogram because it is a sequential statement. Outside a process, you use concurrent statements instead.

beginner

Write a simple VHDL process using a case statement to assign output based on a 2-bit input signal sel.

process(sel) begin case sel is when "00" => output <= '0'; when "01" => output <= '1'; when "10" => output <= '0'; when others => output <= '1'; end case; end process;

What keyword starts a case statement in VHDL inside a process?

A if

B case

C switch

D select

The keyword case is used to start a case statement in VHDL.

Which clause handles all unmatched cases in a VHDL case statement?

A when default

B else

C when others

D otherwise

The when others clause covers all cases not explicitly listed.

Where must a case statement be placed in VHDL?

A Inside a process or subprogram

B Outside any process

C Only in architecture declarative part

D In the package body

Case statements are sequential and must be inside a process or subprogram.

What happens if a case statement misses the 'when others' clause and not all cases are covered?

A Runs last matched case

B Runs with default behavior

C Ignores unmatched cases

D Compilation error

VHDL requires all cases to be covered; missing 'when others' causes a compilation error.

Which of these is a valid case expression type in VHDL?

A An enumerated type

B A real number

C A floating point number

D A string

Case expressions must be discrete types like enumerated types or integers.

Explain how a case statement works inside a VHDL process and why it is useful.

Think about choosing one path among many based on a signal's value.

Write a simple VHDL process using a case statement to assign different outputs for a 3-value input signal.

Start with process(signal) then case signal is, list when options, end case.

Practice

1. What is the main purpose of a case statement inside a VHDL process?

easy

A. To select actions based on the value of a signal

B. To declare new signals inside the process

C. To loop through a range of values

D. To assign default values to all signals

Solution

1. Step 1: Understand the role of case statement

   The case statement chooses different actions depending on the value of a signal.

2. Step 2: Compare with other options

   Declaring signals, looping, or assigning defaults are not the main purpose of case.

3. Final Answer:

   To select actions based on the value of a signal -> Option A

4. Quick Check:

   Case statement = select actions by signal value [OK]

Hint: Case picks actions by signal value inside process [OK]

Common Mistakes:

• Thinking case declares signals
• Confusing case with loops
• Assuming case assigns default values

2. Which of the following is the correct syntax to start a case statement inside a VHDL process for signal sel?

easy

A. switch sel is

B. case (sel) then

C. if sel then

D. case sel is

Solution

1. Step 1: Recall VHDL case syntax

   The correct syntax to start a case statement is case signal_name is.

2. Step 2: Check each option

   case sel is matches the correct syntax. Options A, B, and D are incorrect VHDL syntax.

3. Final Answer:

   case sel is -> Option D

4. Quick Check:

   Correct case syntax = "case signal is" [OK]

Hint: Use 'case signal is' to start a case statement [OK]

Common Mistakes:

• Using 'switch' instead of 'case'
• Adding parentheses or 'then' incorrectly
• Confusing case with if statement

3. Given the following VHDL process, what will be the value of out_signal when sel = "10"?

process(sel)
begin
  case sel is
    when "00" => out_signal <= '0';
    when "01" => out_signal <= '1';
    when "10" => out_signal <= '0';
    when others => out_signal <= '1';
  end case;
end process;

medium

A. '1'

B. Syntax error

C. '0'

D. Undefined

Solution

1. Step 1: Find matching case branch for sel = "10"

   The case statement has a branch when "10" => out_signal <= '0'; which matches the input.

2. Step 2: Determine assigned value

   For sel = "10", out_signal is assigned '0'.

3. Final Answer:

   '0' -> Option C

4. Quick Check:

   sel "10" sets out_signal to '0' [OK]

Hint: Match sel value to case branch to find output [OK]

Common Mistakes:

• Choosing default 'others' branch incorrectly
• Confusing '0' and '1' assignments
• Assuming syntax error without checking code

4. Identify the error in this VHDL process using a case statement:

process(sel)
begin
  case sel is
    when "00" => out_signal <= '0';
    when "01" => out_signal <= '1';
    when others => out_signal <= '0';
  end case;
end process;

medium

A. No error, code is correct

B. Missing semicolon after 'end case'

C. Missing 'when "10"' branch for sel

D. Incorrect use of 'others' keyword

Solution

1. Step 1: Check syntax and completeness

   The case statement covers "00", "01", and uses when others to cover all other values.

2. Step 2: Verify syntax correctness

   Semicolons and keywords are correctly placed; no syntax errors found.

3. Final Answer:

   No error, code is correct -> Option A

4. Quick Check:

   Proper use of 'others' covers missing cases [OK]

Hint: Use 'when others' to cover all missing cases [OK]

Common Mistakes:

• Thinking all cases must be listed explicitly
• Assuming missing branch causes error without 'others'
• Misplacing semicolons

5. You want to design a VHDL process that sets out_signal to '1' only when sel is "01" or "11", and '0' otherwise. Which case statement inside the process correctly implements this?

hard

A. case sel is
when "01" | "11" => out_signal <= '1';
when others => out_signal <= '0';
end case;

B. case sel is
when "01" => out_signal <= '1';
when "11" => out_signal <= '1';
when others => out_signal <= '0';
end case;

C. case sel is
when "01" => out_signal <= '1';
when others => out_signal <= '0';
end case;

D. case sel is
when "01" => out_signal <= '1';
when "10" => out_signal <= '1';
when others => out_signal <= '0';
end case;

Solution

1. Step 1: Identify required conditions

   Set out_signal to '1' only for sel = "01" or sel = "11", else '0'.

2. Step 2: Check each option for correctness

   case sel is when "01" | "11" => out_signal <= '1'; when others => out_signal <= '0'; end case; uses invalid syntax with '|' for multiple choices in VHDL case. case sel is when "01" => out_signal <= '1'; when "11" => out_signal <= '1'; when others => out_signal <= '0'; end case; lists both cases separately, which is correct. case sel is when "01" => out_signal <= '1'; when others => out_signal <= '0'; end case; misses "11" case. case sel is when "01" => out_signal <= '1'; when "10" => out_signal <= '1'; when others => out_signal <= '0'; end case; incorrectly uses "10" instead of "11".

3. Final Answer:

   Option B with separate when clauses for "01" and "11" -> Option B

4. Quick Check:

   Separate when lines for each value = correct VHDL [OK]

Hint: List each case separately; no '|' for multiple values in VHDL [OK]

Common Mistakes:

• Using '|' to combine cases (invalid in VHDL)
• Missing one required case
• Confusing similar bit patterns