Case statement in process in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to start the process block with the correct sensitivity list.

VHDL

process([1])
begin
  -- process body
end process;

Drag options to blanks, or click blank then click option'

Aclk

Breset

Cclk, reset

Ddata_in

Attempts:

3 left

💡 Hint

Common Mistakes

Including only the clock or only the reset signal in the sensitivity list.

The process sensitivity list should include both clk and reset signals to react to changes in either.

2fill in blank

medium

Complete the code to write a case statement that checks the value of the signal state.

VHDL

case [1] is
  when IDLE =>
    -- actions
  when RUN =>
    -- actions
  when others =>
    -- default actions
end case;

Drag options to blanks, or click blank then click option'

Areset

Bstate

Cclk

Dinput_signal

Attempts:

3 left

💡 Hint

Common Mistakes

Using a signal like clk or reset instead of state in the case statement.

The case statement should evaluate the state signal to decide which branch to execute.

3fill in blank

hard

Fix the error in the case statement to correctly assign output_signal when state is RUN.

VHDL

case state is
  when IDLE =>
    output_signal <= '0';
  when RUN =>
    output_signal <= [1];
  when others =>
    output_signal <= '0';
end case;

Drag options to blanks, or click blank then click option'

A'1'

B1

C"1"

D'0'

Attempts:

3 left

💡 Hint

Common Mistakes

Using double quotes or numeric 1 instead of character literal '1'.

In VHDL, single quotes '1' are used for single bit values. Double quotes are for strings.

4fill in blank

hard

Fill both blanks to complete the process with a case statement that handles state and assigns output_signal accordingly.

VHDL

process(clk, reset)
begin
  if reset = '1' then
    output_signal <= '0';
  elsif rising_edge(clk) then
    case [1] is
      when IDLE =>
        output_signal <= '0';
      when RUN =>
        output_signal <= [2];
      when others =>
        output_signal <= '0';
    end case;
  end if;
end process;

Drag options to blanks, or click blank then click option'

Astate

B'1'

C'0'

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using the clock signal in the case statement or assigning numeric 1 instead of '1'.

The case statement should check the state signal, and when RUN, assign '1' to output_signal.

5fill in blank

hard

Fill all three blanks to complete a process with a case statement that resets and updates output_signal based on state.

VHDL

process([1])
begin
  if [2] = '1' then
    output_signal <= '0';
  elsif rising_edge(clk) then
    case state is
      when IDLE =>
        output_signal <= '0';
      when RUN =>
        output_signal <= [3];
      when others =>
        output_signal <= '0';
    end case;
  end if;
end process;

Drag options to blanks, or click blank then click option'

Aclk, reset

Breset

C'1'

D'0'

Attempts:

3 left

💡 Hint

Common Mistakes

Missing reset in sensitivity list or using wrong quotes for bit values.

The process sensitivity list includes clk and reset. The reset condition checks reset signal. When in RUN state, output_signal is set to '1'.

Practice

1. What is the main purpose of a case statement inside a VHDL process?

easy

A. To select actions based on the value of a signal

B. To declare new signals inside the process

C. To loop through a range of values

D. To assign default values to all signals

Solution

1. Step 1: Understand the role of case statement

   The case statement chooses different actions depending on the value of a signal.

2. Step 2: Compare with other options

   Declaring signals, looping, or assigning defaults are not the main purpose of case.

3. Final Answer:

   To select actions based on the value of a signal -> Option A

4. Quick Check:

   Case statement = select actions by signal value [OK]

Hint: Case picks actions by signal value inside process [OK]

Common Mistakes:

• Thinking case declares signals
• Confusing case with loops
• Assuming case assigns default values

2. Which of the following is the correct syntax to start a case statement inside a VHDL process for signal sel?

easy

A. switch sel is

B. case (sel) then

C. if sel then

D. case sel is

Solution

1. Step 1: Recall VHDL case syntax

   The correct syntax to start a case statement is case signal_name is.

2. Step 2: Check each option

   case sel is matches the correct syntax. Options A, B, and D are incorrect VHDL syntax.

3. Final Answer:

   case sel is -> Option D

4. Quick Check:

   Correct case syntax = "case signal is" [OK]

Hint: Use 'case signal is' to start a case statement [OK]

Common Mistakes:

• Using 'switch' instead of 'case'
• Adding parentheses or 'then' incorrectly
• Confusing case with if statement

3. Given the following VHDL process, what will be the value of out_signal when sel = "10"?

process(sel)
begin
  case sel is
    when "00" => out_signal <= '0';
    when "01" => out_signal <= '1';
    when "10" => out_signal <= '0';
    when others => out_signal <= '1';
  end case;
end process;

medium

A. '1'

B. Syntax error

C. '0'

D. Undefined

Solution

1. Step 1: Find matching case branch for sel = "10"

   The case statement has a branch when "10" => out_signal <= '0'; which matches the input.

2. Step 2: Determine assigned value

   For sel = "10", out_signal is assigned '0'.

3. Final Answer:

   '0' -> Option C

4. Quick Check:

   sel "10" sets out_signal to '0' [OK]

Hint: Match sel value to case branch to find output [OK]

Common Mistakes:

• Choosing default 'others' branch incorrectly
• Confusing '0' and '1' assignments
• Assuming syntax error without checking code

4. Identify the error in this VHDL process using a case statement:

process(sel)
begin
  case sel is
    when "00" => out_signal <= '0';
    when "01" => out_signal <= '1';
    when others => out_signal <= '0';
  end case;
end process;

medium

A. No error, code is correct

B. Missing semicolon after 'end case'

C. Missing 'when "10"' branch for sel

D. Incorrect use of 'others' keyword

Solution

1. Step 1: Check syntax and completeness

   The case statement covers "00", "01", and uses when others to cover all other values.

2. Step 2: Verify syntax correctness

   Semicolons and keywords are correctly placed; no syntax errors found.

3. Final Answer:

   No error, code is correct -> Option A

4. Quick Check:

   Proper use of 'others' covers missing cases [OK]

Hint: Use 'when others' to cover all missing cases [OK]

Common Mistakes:

• Thinking all cases must be listed explicitly
• Assuming missing branch causes error without 'others'
• Misplacing semicolons

5. You want to design a VHDL process that sets out_signal to '1' only when sel is "01" or "11", and '0' otherwise. Which case statement inside the process correctly implements this?

hard

A. case sel is
when "01" | "11" => out_signal <= '1';
when others => out_signal <= '0';
end case;

B. case sel is
when "01" => out_signal <= '1';
when "11" => out_signal <= '1';
when others => out_signal <= '0';
end case;

C. case sel is
when "01" => out_signal <= '1';
when others => out_signal <= '0';
end case;

D. case sel is
when "01" => out_signal <= '1';
when "10" => out_signal <= '1';
when others => out_signal <= '0';
end case;

Solution

1. Step 1: Identify required conditions

   Set out_signal to '1' only for sel = "01" or sel = "11", else '0'.

2. Step 2: Check each option for correctness

   case sel is when "01" | "11" => out_signal <= '1'; when others => out_signal <= '0'; end case; uses invalid syntax with '|' for multiple choices in VHDL case. case sel is when "01" => out_signal <= '1'; when "11" => out_signal <= '1'; when others => out_signal <= '0'; end case; lists both cases separately, which is correct. case sel is when "01" => out_signal <= '1'; when others => out_signal <= '0'; end case; misses "11" case. case sel is when "01" => out_signal <= '1'; when "10" => out_signal <= '1'; when others => out_signal <= '0'; end case; incorrectly uses "10" instead of "11".

3. Final Answer:

   Option B with separate when clauses for "01" and "11" -> Option B

4. Quick Check:

   Separate when lines for each value = correct VHDL [OK]

Hint: List each case separately; no '|' for multiple values in VHDL [OK]

Common Mistakes:

• Using '|' to combine cases (invalid in VHDL)
• Missing one required case
• Confusing similar bit patterns