Case statement in process in VHDL - Mini Project: Build & Apply

Using Case Statement Inside a Process in VHDL

📖 Scenario: You are designing a simple digital circuit that outputs different signals based on a 2-bit input. This is like a traffic light controller that changes lights based on a selector switch.

🎯 Goal: Build a VHDL process that uses a case statement to set output signals depending on a 2-bit input value.

📋 What You'll Learn

Create a 2-bit input signal called selector

Create a 1-bit output signal called light

Create a process that triggers on changes to selector

Inside the process, use a case statement on selector

Set light to '1' or '0' based on selector values

Include a when others clause to handle unexpected values

💡 Why This Matters

🌍 Real World

Case statements inside processes are used in digital circuits to select different outputs based on input signals, like controlling lights, motors, or other devices.

💼 Career

Understanding case statements in VHDL processes is essential for hardware engineers and FPGA developers who design and test digital logic circuits.

1

Create input and output signals

Write the VHDL code to declare a 2-bit input signal called selector and a 1-bit output signal called light inside an entity named TrafficLight.

VHDL

entity TrafficLight is
    Port (
        selector : in std_logic_vector(1 downto 0);
        light : out std_logic
    );
end TrafficLight;

architecture Behavioral of TrafficLight is
begin
    -- Your code here
end Behavioral;

Hint

Remember to declare selector as std_logic_vector(1 downto 0) and light as std_logic in the entity port.

2

Add a process triggered by selector

Inside the Behavioral architecture, write a process named light_control that is sensitive to selector.

VHDL

entity TrafficLight is
    Port (
        selector : in std_logic_vector(1 downto 0);
        light : out std_logic
    );
end TrafficLight;

architecture Behavioral of TrafficLight is
begin
    light_control: process(selector)
    begin
        -- Your code here
    end process light_control;
end Behavioral;

Hint

Use process(selector) to trigger on changes to selector. Name the process light_control.

3

Use a case statement inside the process

Inside the light_control process, write a case statement on selector with these rules: when "00" set light to '0', when "01" set light to '1', when "10" set light to '0', when "11" set light to '1', and use when others to set light to '0'.

VHDL

entity TrafficLight is
    Port (
        selector : in std_logic_vector(1 downto 0);
        light : out std_logic
    );
end TrafficLight;

architecture Behavioral of TrafficLight is
begin
    light_control: process(selector)
    begin
        case selector is
            when "00" =>
                -- Your code here
            when "01" =>
                -- Your code here
            when "10" =>
                -- Your code here
            when "11" =>
                -- Your code here
            when others =>
                -- Your code here
        end case;
    end process light_control;
end Behavioral;

Hint

Use case selector is and set light using <= inside each when branch.

4

Simulate and output the light signal

Add a simple testbench process inside the architecture to print the value of light for each selector value from "00" to "11". Use report statements to display the output.

VHDL

entity TrafficLight is
    Port (
        selector : in std_logic_vector(1 downto 0);
        light : out std_logic
    );
end TrafficLight;

architecture Behavioral of TrafficLight is
begin
    light_control: process(selector)
    begin
        case selector is
            when "00" =>
                light 
                light 
                light 
                light 
                light <= '0';
        end case;
    end process light_control;

    test_process: process
    begin
        -- Your code here
    end process test_process;
end Behavioral;

Hint

Use a for loop from 0 to 3, assign selector using std_logic_vector(to_unsigned(i, 2)), wait 10 ns, then report the values.

Practice

1. What is the main purpose of a case statement inside a VHDL process?

easy

A. To select actions based on the value of a signal

B. To declare new signals inside the process

C. To loop through a range of values

D. To assign default values to all signals

Solution

1. Step 1: Understand the role of case statement

   The case statement chooses different actions depending on the value of a signal.

2. Step 2: Compare with other options

   Declaring signals, looping, or assigning defaults are not the main purpose of case.

3. Final Answer:

   To select actions based on the value of a signal -> Option A

4. Quick Check:

   Case statement = select actions by signal value [OK]

Hint: Case picks actions by signal value inside process [OK]

Common Mistakes:

• Thinking case declares signals
• Confusing case with loops
• Assuming case assigns default values

2. Which of the following is the correct syntax to start a case statement inside a VHDL process for signal sel?

easy

A. switch sel is

B. case (sel) then

C. if sel then

D. case sel is

Solution

1. Step 1: Recall VHDL case syntax

   The correct syntax to start a case statement is case signal_name is.

2. Step 2: Check each option

   case sel is matches the correct syntax. Options A, B, and D are incorrect VHDL syntax.

3. Final Answer:

   case sel is -> Option D

4. Quick Check:

   Correct case syntax = "case signal is" [OK]

Hint: Use 'case signal is' to start a case statement [OK]

Common Mistakes:

• Using 'switch' instead of 'case'
• Adding parentheses or 'then' incorrectly
• Confusing case with if statement

3. Given the following VHDL process, what will be the value of out_signal when sel = "10"?

process(sel)
begin
  case sel is
    when "00" => out_signal <= '0';
    when "01" => out_signal <= '1';
    when "10" => out_signal <= '0';
    when others => out_signal <= '1';
  end case;
end process;

medium

A. '1'

B. Syntax error

C. '0'

D. Undefined

Solution

1. Step 1: Find matching case branch for sel = "10"

   The case statement has a branch when "10" => out_signal <= '0'; which matches the input.

2. Step 2: Determine assigned value

   For sel = "10", out_signal is assigned '0'.

3. Final Answer:

   '0' -> Option C

4. Quick Check:

   sel "10" sets out_signal to '0' [OK]

Hint: Match sel value to case branch to find output [OK]

Common Mistakes:

• Choosing default 'others' branch incorrectly
• Confusing '0' and '1' assignments
• Assuming syntax error without checking code

4. Identify the error in this VHDL process using a case statement:

process(sel)
begin
  case sel is
    when "00" => out_signal <= '0';
    when "01" => out_signal <= '1';
    when others => out_signal <= '0';
  end case;
end process;

medium

A. No error, code is correct

B. Missing semicolon after 'end case'

C. Missing 'when "10"' branch for sel

D. Incorrect use of 'others' keyword

Solution

1. Step 1: Check syntax and completeness

   The case statement covers "00", "01", and uses when others to cover all other values.

2. Step 2: Verify syntax correctness

   Semicolons and keywords are correctly placed; no syntax errors found.

3. Final Answer:

   No error, code is correct -> Option A

4. Quick Check:

   Proper use of 'others' covers missing cases [OK]

Hint: Use 'when others' to cover all missing cases [OK]

Common Mistakes:

• Thinking all cases must be listed explicitly
• Assuming missing branch causes error without 'others'
• Misplacing semicolons

5. You want to design a VHDL process that sets out_signal to '1' only when sel is "01" or "11", and '0' otherwise. Which case statement inside the process correctly implements this?

hard

A. case sel is
when "01" | "11" => out_signal <= '1';
when others => out_signal <= '0';
end case;

B. case sel is
when "01" => out_signal <= '1';
when "11" => out_signal <= '1';
when others => out_signal <= '0';
end case;

C. case sel is
when "01" => out_signal <= '1';
when others => out_signal <= '0';
end case;

D. case sel is
when "01" => out_signal <= '1';
when "10" => out_signal <= '1';
when others => out_signal <= '0';
end case;

Solution

1. Step 1: Identify required conditions

   Set out_signal to '1' only for sel = "01" or sel = "11", else '0'.

2. Step 2: Check each option for correctness

   case sel is when "01" | "11" => out_signal <= '1'; when others => out_signal <= '0'; end case; uses invalid syntax with '|' for multiple choices in VHDL case. case sel is when "01" => out_signal <= '1'; when "11" => out_signal <= '1'; when others => out_signal <= '0'; end case; lists both cases separately, which is correct. case sel is when "01" => out_signal <= '1'; when others => out_signal <= '0'; end case; misses "11" case. case sel is when "01" => out_signal <= '1'; when "10" => out_signal <= '1'; when others => out_signal <= '0'; end case; incorrectly uses "10" instead of "11".

3. Final Answer:

   Option B with separate when clauses for "01" and "11" -> Option B

4. Quick Check:

   Separate when lines for each value = correct VHDL [OK]

Hint: List each case separately; no '|' for multiple values in VHDL [OK]

Common Mistakes:

• Using '|' to combine cases (invalid in VHDL)
• Missing one required case
• Confusing similar bit patterns