Case statement in process in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple case statement in a process

What is the value of y after the process runs with sel = "10"?

VHDL

architecture Behavioral of case_example is
  signal sel : std_logic_vector(1 downto 0) := "10";
  signal y : integer := 0;
begin
  process(sel)
  begin
    case sel is
      when "00" => y <= 1;
      when "01" => y <= 2;
      when "10" => y <= 3;
      when others => y <= 0;
    end case;
  end process;
end Behavioral;

A y = 3

B y = 0

C y = 2

D y = 1

💡 Hint

Check which when branch matches the value of sel.

The sel signal is "10", so the case branch when "10" executes, setting y to 3.

❓ Predict Output

intermediate

Case statement with overlapping choices

What will be the value of out_signal after the process executes if input_val = '1'?

VHDL

architecture Behavioral of overlap_case is
  signal input_val : std_logic := '1';
  signal out_signal : integer := 0;
begin
  process(input_val)
  begin
    case input_val is
      when '0' => out_signal <= 10;
      when '1' => out_signal <= 20;
      when others => out_signal <= 30;
    end case;
  end process;
end Behavioral;

A out_signal = 0

B out_signal = 20

C out_signal = 30

D out_signal = 10

💡 Hint

Match the input_val with the correct when branch.

Since input_val is '1', the case branch when '1' sets out_signal to 20.

🔧 Debug

advanced

Identify the error in this case statement inside a process

What error will this VHDL code produce when compiled?

VHDL

architecture Behavioral of error_case is
  signal sel : std_logic_vector(1 downto 0);
  signal y : integer := 0;
begin
  process(sel)
  begin
    case sel is
      when "00" => y <= 1;
      when "01" => y <= 2;
      when "10" => y <= 3;
      -- Missing when others branch
    end case;
  end process;
end Behavioral;

A Syntax error: missing semicolon after case statement

B Runtime error: y is not assigned for some sel values

C No error, code compiles and runs fine

D Compilation error: case statement missing 'when others' branch

💡 Hint

Check if the case statement covers all possible values of sel.

In VHDL, a case statement must cover all possible values. Missing the when others branch causes a compilation error.

❓ Predict Output

advanced

Output of nested case statements in a process

Given mode = "01" and state = "10", what is the value of result after the process runs?

VHDL

architecture Behavioral of nested_case is
  signal mode : std_logic_vector(1 downto 0) := "01";
  signal state : std_logic_vector(1 downto 0) := "10";
  signal result : integer := 0;
begin
  process(mode, state)
  begin
    case mode is
      when "00" => result <= 100;
      when "01" =>
        case state is
          when "00" => result <= 200;
          when "10" => result <= 300;
          when others => result <= 400;
        end case;
      when others => result <= 500;
    end case;
  end process;
end Behavioral;

A result = 300

B result = 200

C result = 400

D result = 500

💡 Hint

Follow the outer case on mode and then the inner case on state.

Outer case matches mode = "01", then inner case matches state = "10", so result is set to 300.

❓ Predict Output

expert

Value of signal after process with case and signal update timing

Consider this process with signal assignments. What is the value of z after the process completes if input = "11"?

VHDL

architecture Behavioral of timing_case is
  signal input : std_logic_vector(1 downto 0) := "11";
  signal z : integer := 0;
begin
  process(input)
  begin
    case input is
      when "00" => z <= 5;
      when "11" =>
        z <= z + 1;
      when others => z <= 0;
    end case;
  end process;
end Behavioral;

A z = 5

B z = 0

C z = 1

D z = undefined (simulation error)

💡 Hint

Remember that signal updates inside a process take effect after the process completes.

The signal z is read before the process starts, so z + 1 uses the old value 0, and the new value 1 is scheduled but not visible inside the process. After the process, z becomes 1.

Practice

1. What is the main purpose of a case statement inside a VHDL process?

easy

A. To select actions based on the value of a signal

B. To declare new signals inside the process

C. To loop through a range of values

D. To assign default values to all signals

Solution

1. Step 1: Understand the role of case statement

   The case statement chooses different actions depending on the value of a signal.

2. Step 2: Compare with other options

   Declaring signals, looping, or assigning defaults are not the main purpose of case.

3. Final Answer:

   To select actions based on the value of a signal -> Option A

4. Quick Check:

   Case statement = select actions by signal value [OK]

Hint: Case picks actions by signal value inside process [OK]

Common Mistakes:

• Thinking case declares signals
• Confusing case with loops
• Assuming case assigns default values

2. Which of the following is the correct syntax to start a case statement inside a VHDL process for signal sel?

easy

A. switch sel is

B. case (sel) then

C. if sel then

D. case sel is

Solution

1. Step 1: Recall VHDL case syntax

   The correct syntax to start a case statement is case signal_name is.

2. Step 2: Check each option

   case sel is matches the correct syntax. Options A, B, and D are incorrect VHDL syntax.

3. Final Answer:

   case sel is -> Option D

4. Quick Check:

   Correct case syntax = "case signal is" [OK]

Hint: Use 'case signal is' to start a case statement [OK]

Common Mistakes:

• Using 'switch' instead of 'case'
• Adding parentheses or 'then' incorrectly
• Confusing case with if statement

3. Given the following VHDL process, what will be the value of out_signal when sel = "10"?

process(sel)
begin
  case sel is
    when "00" => out_signal <= '0';
    when "01" => out_signal <= '1';
    when "10" => out_signal <= '0';
    when others => out_signal <= '1';
  end case;
end process;

medium

A. '1'

B. Syntax error

C. '0'

D. Undefined

Solution

1. Step 1: Find matching case branch for sel = "10"

   The case statement has a branch when "10" => out_signal <= '0'; which matches the input.

2. Step 2: Determine assigned value

   For sel = "10", out_signal is assigned '0'.

3. Final Answer:

   '0' -> Option C

4. Quick Check:

   sel "10" sets out_signal to '0' [OK]

Hint: Match sel value to case branch to find output [OK]

Common Mistakes:

• Choosing default 'others' branch incorrectly
• Confusing '0' and '1' assignments
• Assuming syntax error without checking code

4. Identify the error in this VHDL process using a case statement:

process(sel)
begin
  case sel is
    when "00" => out_signal <= '0';
    when "01" => out_signal <= '1';
    when others => out_signal <= '0';
  end case;
end process;

medium

A. No error, code is correct

B. Missing semicolon after 'end case'

C. Missing 'when "10"' branch for sel

D. Incorrect use of 'others' keyword

Solution

1. Step 1: Check syntax and completeness

   The case statement covers "00", "01", and uses when others to cover all other values.

2. Step 2: Verify syntax correctness

   Semicolons and keywords are correctly placed; no syntax errors found.

3. Final Answer:

   No error, code is correct -> Option A

4. Quick Check:

   Proper use of 'others' covers missing cases [OK]

Hint: Use 'when others' to cover all missing cases [OK]

Common Mistakes:

• Thinking all cases must be listed explicitly
• Assuming missing branch causes error without 'others'
• Misplacing semicolons

5. You want to design a VHDL process that sets out_signal to '1' only when sel is "01" or "11", and '0' otherwise. Which case statement inside the process correctly implements this?

hard

A. case sel is
when "01" | "11" => out_signal <= '1';
when others => out_signal <= '0';
end case;

B. case sel is
when "01" => out_signal <= '1';
when "11" => out_signal <= '1';
when others => out_signal <= '0';
end case;

C. case sel is
when "01" => out_signal <= '1';
when others => out_signal <= '0';
end case;

D. case sel is
when "01" => out_signal <= '1';
when "10" => out_signal <= '1';
when others => out_signal <= '0';
end case;

Solution

1. Step 1: Identify required conditions

   Set out_signal to '1' only for sel = "01" or sel = "11", else '0'.

2. Step 2: Check each option for correctness

   case sel is when "01" | "11" => out_signal <= '1'; when others => out_signal <= '0'; end case; uses invalid syntax with '|' for multiple choices in VHDL case. case sel is when "01" => out_signal <= '1'; when "11" => out_signal <= '1'; when others => out_signal <= '0'; end case; lists both cases separately, which is correct. case sel is when "01" => out_signal <= '1'; when others => out_signal <= '0'; end case; misses "11" case. case sel is when "01" => out_signal <= '1'; when "10" => out_signal <= '1'; when others => out_signal <= '0'; end case; incorrectly uses "10" instead of "11".

3. Final Answer:

   Option B with separate when clauses for "01" and "11" -> Option B

4. Quick Check:

   Separate when lines for each value = correct VHDL [OK]

Hint: List each case separately; no '|' for multiple values in VHDL [OK]

Common Mistakes:

• Using '|' to combine cases (invalid in VHDL)
• Missing one required case
• Confusing similar bit patterns