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VHDLprogramming~10 mins

Why operators model combinational logic behavior in VHDL - Test Your Understanding

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Practice - 5 Tasks
Answer the questions below
1fill in blank
easy

Complete the code to assign the output as the AND of inputs A and B.

VHDL
output_signal <= input_a [1] input_b;
Drag options to blanks, or click blank then click option'
Anand
Bor
Cxor
Dand
Attempts:
3 left
💡 Hint
Common Mistakes
Using 'or' instead of 'and' changes the logic behavior.
2fill in blank
medium

Complete the code to assign output as the OR of inputs A and B.

VHDL
output_signal <= input_a [1] input_b;
Drag options to blanks, or click blank then click option'
Aor
Bnand
Cxor
Dand
Attempts:
3 left
💡 Hint
Common Mistakes
Using 'and' instead of 'or' changes the logic behavior.
3fill in blank
hard

Fix the error in the code to correctly assign output as XOR of inputs A and B.

VHDL
output_signal <= input_a [1] input_b;
Drag options to blanks, or click blank then click option'
Axor
Bnand
Cor
Dand
Attempts:
3 left
💡 Hint
Common Mistakes
Using 'or' or 'and' instead of 'xor' changes the logic behavior.
4fill in blank
hard

Fill both blanks to create a combinational expression that outputs 1 only when both inputs are 1 and then inverts the result.

VHDL
output_signal <= [2] (input_a [1] input_b);
Drag options to blanks, or click blank then click option'
Aand
Bor
Cnot
Dxor
Attempts:
3 left
💡 Hint
Common Mistakes
Using 'or' instead of 'and' changes the logic.
5fill in blank
hard

Fill both blanks to create a combinational expression that outputs 1 when input_a is 1, input_b is 0, and input_c is 1.

VHDL
output_signal <= (input_a [1] (not input_b)) [2] input_c;
Drag options to blanks, or click blank then click option'
Aand
Bor
Cxor
Dnand
Attempts:
3 left
💡 Hint
Common Mistakes
Using OR or XOR changes the logic behavior.