VHDL vs Verilog comparison - Interactive Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a signal in VHDL.

VHDL

signal clk : [1];

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Awire

Bbit

Creg

Dint

Attempts:

3 left

💡 Hint

Common Mistakes

Using Verilog types like 'wire' or 'reg' in VHDL signal declaration.

In VHDL, signals are declared with types like bit or std_logic. bit is a basic type representing 0 or 1.

2fill in blank

medium

Complete the code to assign a value to a signal in VHDL.

VHDL

clk <= [1];

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A'1'

B1'b1

C"1"

D1

Attempts:

3 left

💡 Hint

Common Mistakes

Using Verilog style bit literals like 1'b1 in VHDL.

In VHDL, single quotes '1' are used for bit literals. Double quotes are for bit vectors.

3fill in blank

hard

Fix the error in the VHDL process sensitivity list.

VHDL

process([1])
begin
  -- process body
end process;

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Aclk or reset

Bclk; reset

Cclk, reset

Dclk and reset

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'or' like in Verilog or semicolons instead of commas in sensitivity lists.

In VHDL, signals in the sensitivity list are separated by , (commas), not or like in Verilog.

4fill in blank

hard

Fill both blanks to complete the VHDL entity port declaration.

VHDL

entity my_entity is
  port(
    clk : in [1];
    data : out [2];
  );
end my_entity;

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Astd_logic

Bbit_vector

Cstd_logic_vector

Dinteger

Attempts:

3 left

💡 Hint

Common Mistakes

Using bit_vector which is less common than std_logic_vector.

Mixing types between single bit and vector signals.

clk is usually a single bit signal, so std_logic is used. data is often a bus, so std_logic_vector is appropriate.

5fill in blank

hard

Fill all three blanks to complete the VHDL architecture signal assignment.

VHDL

architecture Behavioral of my_entity is
  signal temp : [1];
begin
  process([2])
  begin
    if rising_edge([3]) then
      temp <= '1';
    end if;
  end process;
end Behavioral;

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Astd_logic

Bclk

Dbit

Attempts:

3 left

💡 Hint

Common Mistakes

Using different names for clock signal in sensitivity list and edge detection.

Declaring signal with wrong type.

The signal temp is declared as std_logic. The process sensitivity list includes clk. The rising edge is detected on clk.