Testbench entity (no ports) in VHDL - Step-by-Step Execution

Concept Flow - Testbench entity (no ports)

Define testbench entity

↓

No ports declared

↓

Architecture body with test process

↓

Simulate signals and behavior

↓

Observe outputs internally

↓

End simulation

A testbench entity in VHDL has no ports and contains an architecture that simulates the design internally.

Execution Sample

VHDL

entity tb_example is
end tb_example;

architecture behavior of tb_example is
begin
  process
  begin
    -- test stimulus here
    wait;
  end process;
end behavior;

Defines a testbench entity with no ports and a process that runs simulation stimulus.

Execution Table

Step	Action	Evaluation	Result
1	Start simulation	Entity tb_example recognized	No ports, ready to simulate internally
2	Enter architecture behavior	Begin process execution	Process starts running
3	Execute test stimulus	No signals changed (placeholder)	Wait statement halts process
4	Simulation waits indefinitely	No further actions	Simulation runs until manually stopped

💡 Simulation stops manually since wait statement halts process indefinitely

Variable Tracker

Variable	Start	After Step 2	After Step 3	Final
process_state	not started	running	waiting	waiting

Key Moments - 2 Insights

Why does the testbench entity have no ports?

Because it is a top-level simulation unit that drives signals internally, no external connections are needed (see execution_table step 1).

What does the 'wait;' statement do in the process?

It pauses the process indefinitely, stopping further simulation steps until manually stopped (see execution_table step 3 and 4).

Visual Quiz - 3 Questions

Look at the execution table, what is the process state after step 3?

A running

B not started

C waiting

D finished

💡 Hint

Check variable_tracker row 'process_state' after step 3

At which step does the simulation enter an indefinite wait?

A Step 1

B Step 3

C Step 2

D Step 4

💡 Hint

See execution_table action 'Execute test stimulus' with wait statement

If the testbench had ports, how would the execution flow change?

A It would simulate external inputs and outputs

B It would not run any process

C It would stop at entity declaration

D It would require manual signal assignment

💡 Hint

Ports allow interaction with external signals, changing simulation behavior

Concept Snapshot

Testbench entity has no ports
Contains architecture with processes
Processes generate test signals internally
Uses 'wait;' to pause simulation
No external connections needed
Simulation runs until manually stopped

Full Transcript

A testbench entity in VHDL is defined without any ports because it acts as the top-level simulation unit. Inside its architecture, it contains processes that generate test signals and simulate the design behavior. The process often includes a 'wait;' statement to pause the simulation indefinitely, allowing observation of internal signals. The simulation runs until manually stopped. This setup helps test the design without external connections.