Report statement for debug output in VHDL - Step-by-Step Execution

Concept Flow - Report statement for debug output

Start Simulation

↓

Execute VHDL Process

↓

Encounter Report Statement

↓

Display Message on Console

↓

Continue Simulation or Stop if Severity is FAILURE

The report statement outputs a message during simulation for debugging, optionally stopping simulation on severe errors.

Execution Sample

VHDL

process
begin
  report "Starting process" severity note;
  wait for 10 ns;
  report "Process completed" severity warning;
  wait;
end process;

This code prints debug messages at different severity levels during simulation.

Execution Table

Step	Action	Report Message	Severity	Simulation Effect
1	Start process execution			Simulation runs
2	Execute report statement	Starting process	note	Message printed, simulation continues
3	Wait for 10 ns			Simulation waits 10 ns
4	Execute report statement	Process completed	warning	Message printed, simulation continues
5	Wait indefinitely			Simulation waits forever
6	End of process			Process suspended, simulation continues

💡 Simulation continues unless severity is FAILURE or ERROR

Variable Tracker

Variable	Start	After Step 2	After Step 4	Final
Simulation Time (ns)	0	0	10	10
Last Report Message	""	"Starting process"	"Process completed"	"Process completed"
Last Severity	""	note	warning	warning

Key Moments - 2 Insights

Why does the simulation not stop after the report statement with severity warning?

Because only severity levels ERROR or FAILURE stop simulation; WARNING and NOTE just print messages and continue, as shown in steps 2 and 4.

What happens if severity is FAILURE in a report statement?

Simulation stops immediately after printing the message, unlike the WARNING or NOTE severities seen in the execution table.

Visual Quiz - 3 Questions

Look at the execution table, what is the simulation time after the first report statement?

A 0 ns

B 10 ns

C After wait

D Indefinite

💡 Hint

Check the 'Simulation Time (ns)' row in variable_tracker after Step 2.

At which step does the simulation wait for 10 ns?

A Step 2

B Step 4

C Step 3

D Step 5

💡 Hint

Look at the 'Action' column in execution_table for waiting periods.

If the severity in the second report was FAILURE, what would happen?

A Simulation continues normally

B Simulation prints message and stops

C Message is not printed

D Simulation pauses but does not stop

💡 Hint

Refer to key_moments about severity effects on simulation.

Concept Snapshot

VHDL report statement syntax:
report "message" severity level;
Severity levels: NOTE, WARNING, ERROR, FAILURE.
NOTE and WARNING print messages and continue simulation.
ERROR and FAILURE print messages and stop simulation.
Used for debug output during simulation.

Full Transcript

The VHDL report statement is used to print messages during simulation for debugging. It has a severity level that controls whether simulation continues or stops. Severity levels NOTE and WARNING print messages but allow simulation to continue, while ERROR and FAILURE stop simulation after printing. In the example, two report statements print messages at NOTE and WARNING levels, so simulation continues. The execution table shows each step, including message printing and waiting. Variables like simulation time and last message update accordingly. Understanding severity effects helps control simulation flow during debugging.