Arithmetic operators in VHDL - Mini Project: Build & Apply

Arithmetic Operators in VHDL

📖 Scenario: You are designing a simple digital circuit that performs basic arithmetic operations on two 4-bit numbers. This is common in digital electronics where addition, subtraction, multiplication, and division are needed.

🎯 Goal: Build a VHDL program that defines two 4-bit numbers, sets a control signal to select an arithmetic operation, performs the operation using arithmetic operators, and outputs the result.

📋 What You'll Learn

Create two 4-bit unsigned signals named a and b with exact values "0011" and "0101" respectively.

Create a signal operation of type std_logic_vector(1 downto 0) to select the arithmetic operation.

Use a case statement on operation to perform addition, subtraction, multiplication, or division on a and b.

Output the result as a 8-bit unsigned signal named result.

Print the result value as a binary string in the simulation output.

💡 Why This Matters

🌍 Real World

Digital circuits like calculators, ALUs (Arithmetic Logic Units), and embedded systems use arithmetic operators to perform calculations on binary numbers.

💼 Career

Understanding arithmetic operators in VHDL is essential for FPGA and ASIC design engineers who build digital hardware for computers, communication devices, and control systems.

1

Define the 4-bit unsigned signals a and b

Create two signals called a and b of type unsigned(3 downto 0) with values "0011" and "0101" respectively inside the architecture.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ArithmeticOps is
    port();
end ArithmeticOps;

architecture Behavioral of ArithmeticOps is
    signal a : unsigned(3 downto 0);
    signal b : unsigned(3 downto 0);
begin
    -- Your code here
end Behavioral;

Need a hint?

Use signal a : unsigned(3 downto 0) := "0011"; and similarly for b.

2

Add a signal operation to select the arithmetic operation

Add a signal called operation of type std_logic_vector(1 downto 0) inside the architecture and initialize it to "00".

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ArithmeticOps is
    port();
end ArithmeticOps;

architecture Behavioral of ArithmeticOps is
    signal a : unsigned(3 downto 0) := "0011";
    signal b : unsigned(3 downto 0) := "0101";
    signal operation : std_logic_vector(1 downto 0);
begin
    -- Your code here
end Behavioral;

Need a hint?

Define operation as std_logic_vector(1 downto 0) and set it to "00".

3

Use a case statement to perform arithmetic based on operation

Inside the architecture, declare a signal result of type unsigned(7 downto 0). Then write a process that uses a case statement on operation to perform addition ("00"), subtraction ("01"), multiplication ("10"), or division ("11") on a and b. Assign the result to result. Use resize to adjust sizes as needed.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ArithmeticOps is
    port();
end ArithmeticOps;

architecture Behavioral of ArithmeticOps is
    signal a : unsigned(3 downto 0) := "0011";
    signal b : unsigned(3 downto 0) := "0101";
    signal operation : std_logic_vector(1 downto 0) := "00";
    signal result : unsigned(7 downto 0);
begin
    process(a, b, operation)
    begin
        case operation is
            when "00" =>
                -- addition
            when "01" =>
                -- subtraction
            when "10" =>
                -- multiplication
            when "11" =>
                -- division
            when others =>
                result  '0');
        end case
    end process;
end Behavioral;

Need a hint?

Use resize from ieee.numeric_std to convert a and b to 8 bits before arithmetic. Use a case on operation to select the operator.

4

Print the result as a binary string

Add a process that prints the result as a binary string using report statement whenever result changes. Use to_string from ieee.numeric_std to convert result to string.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ArithmeticOps is
    port();
end ArithmeticOps;

architecture Behavioral of ArithmeticOps is
    signal a : unsigned(3 downto 0) := "0011";
    signal b : unsigned(3 downto 0) := "0101";
    signal operation : std_logic_vector(1 downto 0) := "00";
    signal result : unsigned(7 downto 0);
begin
    process(a, b, operation)
    begin
        case operation is
            when "00" =>
                result 
                result 
                result 
                if b /= 0 then
                    result  '0');
                end if;
            when others =>
                result  '0');
        end case
    end process;

    -- Your code here
end Behavioral;

Need a hint?

Use a process sensitive to result and a report statement with to_string(result) to print the binary result.