Arithmetic operators in VHDL - Mini Project: Build & Apply

Arithmetic Operators in VHDL

📖 Scenario: You are designing a simple digital circuit that performs basic arithmetic operations on two 4-bit numbers. This is common in digital electronics where addition, subtraction, multiplication, and division are needed.

🎯 Goal: Build a VHDL program that defines two 4-bit numbers, sets a control signal to select an arithmetic operation, performs the operation using arithmetic operators, and outputs the result.

📋 What You'll Learn

Create two 4-bit unsigned signals named a and b with exact values "0011" and "0101" respectively.

Create a signal operation of type std_logic_vector(1 downto 0) to select the arithmetic operation.

Use a case statement on operation to perform addition, subtraction, multiplication, or division on a and b.

Output the result as a 8-bit unsigned signal named result.

Print the result value as a binary string in the simulation output.

💡 Why This Matters

🌍 Real World

Digital circuits like calculators, ALUs (Arithmetic Logic Units), and embedded systems use arithmetic operators to perform calculations on binary numbers.

💼 Career

Understanding arithmetic operators in VHDL is essential for FPGA and ASIC design engineers who build digital hardware for computers, communication devices, and control systems.

1

Define the 4-bit unsigned signals a and b

Create two signals called a and b of type unsigned(3 downto 0) with values "0011" and "0101" respectively inside the architecture.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ArithmeticOps is
    port();
end ArithmeticOps;

architecture Behavioral of ArithmeticOps is
    signal a : unsigned(3 downto 0);
    signal b : unsigned(3 downto 0);
begin
    -- Your code here
end Behavioral;

Hint

Use signal a : unsigned(3 downto 0) := "0011"; and similarly for b.

2

Add a signal operation to select the arithmetic operation

Add a signal called operation of type std_logic_vector(1 downto 0) inside the architecture and initialize it to "00".

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ArithmeticOps is
    port();
end ArithmeticOps;

architecture Behavioral of ArithmeticOps is
    signal a : unsigned(3 downto 0) := "0011";
    signal b : unsigned(3 downto 0) := "0101";
    signal operation : std_logic_vector(1 downto 0);
begin
    -- Your code here
end Behavioral;

Hint

Define operation as std_logic_vector(1 downto 0) and set it to "00".

3

Use a case statement to perform arithmetic based on operation

Inside the architecture, declare a signal result of type unsigned(7 downto 0). Then write a process that uses a case statement on operation to perform addition ("00"), subtraction ("01"), multiplication ("10"), or division ("11") on a and b. Assign the result to result. Use resize to adjust sizes as needed.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ArithmeticOps is
    port();
end ArithmeticOps;

architecture Behavioral of ArithmeticOps is
    signal a : unsigned(3 downto 0) := "0011";
    signal b : unsigned(3 downto 0) := "0101";
    signal operation : std_logic_vector(1 downto 0) := "00";
    signal result : unsigned(7 downto 0);
begin
    process(a, b, operation)
    begin
        case operation is
            when "00" =>
                -- addition
            when "01" =>
                -- subtraction
            when "10" =>
                -- multiplication
            when "11" =>
                -- division
            when others =>
                result  '0');
        end case
    end process;
end Behavioral;

Hint

Use resize from ieee.numeric_std to convert a and b to 8 bits before arithmetic. Use a case on operation to select the operator.

4

Print the result as a binary string

Add a process that prints the result as a binary string using report statement whenever result changes. Use to_string from ieee.numeric_std to convert result to string.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ArithmeticOps is
    port();
end ArithmeticOps;

architecture Behavioral of ArithmeticOps is
    signal a : unsigned(3 downto 0) := "0011";
    signal b : unsigned(3 downto 0) := "0101";
    signal operation : std_logic_vector(1 downto 0) := "00";
    signal result : unsigned(7 downto 0);
begin
    process(a, b, operation)
    begin
        case operation is
            when "00" =>
                result 
                result 
                result 
                if b /= 0 then
                    result  '0');
                end if;
            when others =>
                result  '0');
        end case
    end process;

    -- Your code here
end Behavioral;

Hint

Use a process sensitive to result and a report statement with to_string(result) to print the binary result.

Practice

1. Which of the following is a valid arithmetic operator in VHDL?

easy

A. &&

B. ==

C. +

D. ||

Solution

1. Step 1: Identify common arithmetic operators in VHDL

   VHDL uses +, -, *, /, and mod for arithmetic operations.

2. Step 2: Compare given options with valid operators

   Only + is a valid arithmetic operator; &&, ==, || are logical or comparison operators.

3. Final Answer:

   + -> Option C

4. Quick Check:

   Arithmetic operator = + [OK]

Hint: Remember: +, -, *, /, mod are arithmetic operators [OK]

Common Mistakes:

• Confusing logical operators with arithmetic
• Using == instead of = for comparison
• Thinking && is addition

2. Which of the following is the correct syntax to add two integers a and b in VHDL?

easy

A. c := a plus b;

B. c = a + b;

C. c := a & b;

D. c := a + b;

Solution

1. Step 1: Recall VHDL assignment and addition syntax

   VHDL uses := for assignment and + for addition.

2. Step 2: Check each option for correct syntax

   c := a + b; uses correct assignment and addition syntax; others use invalid keywords or operators.

3. Final Answer:

   c := a + b; -> Option D

4. Quick Check:

   Assignment with := and + operator = c := a + b; [OK]

Hint: Use := for assignment and + for addition in VHDL [OK]

Common Mistakes:

• Using = instead of :=
• Writing 'plus' instead of +
• Using & which is for concatenation

3. What is the result of the following VHDL expression if a = 10 and b = 3?

c := a mod b;

medium

A. 3

B. 1

C. 0

D. 7

Solution

1. Step 1: Understand the mod operator

   The mod operator returns the remainder of division of a by b.

2. Step 2: Calculate 10 mod 3

   10 divided by 3 is 3 with remainder 1, so 10 mod 3 = 1.

3. Final Answer:

   1 -> Option B

4. Quick Check:

   10 mod 3 = 1 [OK]

Hint: mod gives remainder after division [OK]

Common Mistakes:

• Confusing mod with division
• Using / instead of mod
• Calculating 10 - 3 instead of mod

4. Identify the error in this VHDL code snippet:

signal a, b : integer := 5;
signal c : integer;
begin
c := a * b + ;

medium

A. Missing operand after + operator

B. Incorrect signal declaration

C. Using := instead of = for assignment

D. Missing semicolon after signal declarations

Solution

1. Step 1: Analyze the assignment statement

   The expression ends with + but no operand follows it, which is a syntax error.

2. Step 2: Check other parts for errors

   Signal declarations and assignment operator := are correct; semicolons are present.

3. Final Answer:

   Missing operand after + operator -> Option A

4. Quick Check:

   Expression must have operands on both sides of + [OK]

Hint: Check operators have operands on both sides [OK]

Common Mistakes:

• Leaving operator without operand
• Confusing := with =
• Forgetting semicolons

5. Given signals a and b of type integer, write a VHDL expression to calculate the average of a and b using arithmetic operators. Which option is correct?

hard

A. average := (a + b) / 2;

B. average := a + b / 2;

C. average := (a mod b) / 2;

D. average := a * b / 2;

Solution

1. Step 1: Understand how to calculate average

   The average of two numbers is their sum divided by 2.

2. Step 2: Check each expression for correctness

   average := (a + b) / 2; correctly sums a and b first, then divides by 2. Others either miss parentheses or use wrong operators.

3. Final Answer:

   average := (a + b) / 2; -> Option A

4. Quick Check:

   Average = (a + b) / 2 [OK]

Hint: Use parentheses to sum before dividing [OK]

Common Mistakes:

• Missing parentheses changing order
• Using mod instead of +
• Multiplying instead of adding