Synthesizable vs non-synthesizable constructs in VHDL - Interactive Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a signal in VHDL.

VHDL

signal clk : [1];

Drag options to blanks, or click blank then click option'

Astd_logic

Bstring

Cboolean

Dinteger

Attempts:

3 left

💡 Hint

Common Mistakes

Using integer or boolean types for clock signals which are not synthesizable as digital signals.

In VHDL, signals used for hardware description are commonly declared as std_logic.

2fill in blank

medium

Complete the code to write a synthesizable process sensitive to clock and reset.

VHDL

process([1])
begin
  if reset = '1' then
    count <= 0;
  elsif rising_edge(clk) then
    count <= count + 1;
  end if;
end process;

Drag options to blanks, or click blank then click option'

Aclk, reset

Bclk

Creset

Dcount

Attempts:

3 left

💡 Hint

Common Mistakes

Leaving out reset from the sensitivity list causing simulation mismatches.

The process sensitivity list must include both clk and reset signals for proper asynchronous reset behavior.

3fill in blank

hard

Fix the error in the non-synthesizable wait statement inside a process.

VHDL

process
begin
  [1];
  data <= data + 1;
end process;

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Await on clk

Bwait until clk = '1'

Cwait for 10 ns

Dwait

Attempts:

3 left

💡 Hint

Common Mistakes

Using wait statements inside processes intended for synthesis.

Using a plain wait statement inside a process without sensitivity list is non-synthesizable. For synthesis, processes should use sensitivity lists or clocked constructs.

4fill in blank

hard

Fill both blanks to create a synthesizable if statement checking a signal.

VHDL

if [1] = '1' then
  output <= '1';
else
  output <= '0';
end if;

Drag options to blanks, or click blank then click option'

Areset

Bdata

Cenable

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock or reset signals incorrectly in combinational if statements.

The signal enable is typically used to control output in synthesizable logic.

5fill in blank

hard

Fill all three blanks to write a synthesizable case statement for a 2-bit input.

VHDL

case [1] is
  when "00" => output <= [2];
  when "01" => output <= [3];
  when others => output <= '0';
end case;

Drag options to blanks, or click blank then click option'

Asel

B'1'

C'0'

Ddata

Attempts:

3 left

💡 Hint

Common Mistakes

Using data signals instead of selector signals in case statements.

The sel signal is used for selection, and outputs are assigned '1' or '0' accordingly in a synthesizable case statement.

Practice

1. Which of the following VHDL constructs is synthesizable and can be implemented in hardware?

easy

A. Use of assert statements for debugging

B. A process containing wait for 10 ns; statements

C. File I/O operations like reading from a text file

D. A process with only clocked assignments and no wait statements

Solution

1. Step 1: Identify synthesizable constructs

   Synthesizable code must describe hardware behavior, typically using clocked processes without delays or waits.

2. Step 2: Analyze each option

   A process with only clocked assignments and no wait statements uses clocked assignments without waits, so it is synthesizable. Options A, B, and D use waits, assertions, or file I/O, which are non-synthesizable.

3. Final Answer:

   A process with only clocked assignments and no wait statements -> Option D

4. Quick Check:

   Synthesizable = clocked process without wait [OK]

Hint: Synthesizable means no waits or file I/O, just clocked logic [OK]

Common Mistakes:

• Thinking wait statements are synthesizable
• Confusing assert for hardware logic
• Assuming file I/O can be synthesized

2. Which VHDL syntax is not synthesizable?

easy

A. A process with a wait until clk = '1'; statement

B. Concurrent signal assignment outside any process

C. Signal assignment inside a clocked process

D. Using rising_edge(clk) inside a process

Solution

1. Step 1: Understand wait statement restrictions

   Wait statements like wait until clk = '1'; are not synthesizable because hardware cannot implement arbitrary waits.

2. Step 2: Check other options

   Options A, B, and C are standard synthesizable constructs: clock edge detection, signal assignments in processes, and concurrent assignments.

3. Final Answer:

   A process with a wait until clk = '1'; statement -> Option A

4. Quick Check:

   Wait statements = non-synthesizable [OK]

Hint: Wait statements inside processes are never synthesizable [OK]

Common Mistakes:

• Assuming wait until is synthesizable
• Confusing sensitivity list with wait statements
• Thinking concurrent assignments are non-synthesizable

3. What is the output behavior of this VHDL process when synthesized?

process(clk)
begin
  if rising_edge(clk) then
    if reset = '1' then
      q <= '0';
    else
      q <= d;
    end if;
  end if;
end process;

medium

A. q synchronously resets to '0' on clock edge when reset is '1'

B. q asynchronously resets to '0' when reset is '1'

C. q changes immediately when reset is '1', ignoring clock

D. q never resets because reset is ignored

Solution

1. Step 1: Analyze reset behavior inside clocked process

   The reset check is inside the rising_edge(clk) condition, so reset is synchronous.

2. Step 2: Understand output assignment timing

   q is assigned '0' only on clock edge when reset is '1', otherwise q follows d on clock edges.

3. Final Answer:

   q synchronously resets to '0' on clock edge when reset is '1' -> Option A

4. Quick Check:

   Synchronous reset inside clock edge = q synchronously resets to '0' on clock edge when reset is '1' [OK]

Hint: Reset inside rising_edge means synchronous reset [OK]

Common Mistakes:

• Thinking reset is asynchronous here
• Assuming q changes immediately without clock
• Ignoring the rising_edge condition

4. Identify the error in this VHDL code snippet that prevents synthesis:

process(clk)
begin
  wait until clk = '1';
  q <= d;
end process;

medium

A. Signal assignment outside process

B. Missing sensitivity list in process

C. Using wait statement inside a clocked process

D. Incorrect use of <= operator

Solution

1. Step 1: Check for wait statement usage

   Wait statements inside processes are not synthesizable and cause synthesis errors.

2. Step 2: Verify other syntax elements

   The process has a sensitivity list (clk), signal assignment is inside process, and <= is correctly used.

3. Final Answer:

   Using wait statement inside a clocked process -> Option C

4. Quick Check:

   Wait inside process = synthesis error [OK]

Hint: Wait statements inside processes cause synthesis errors [OK]

Common Mistakes:

• Ignoring that wait is not synthesizable
• Confusing sensitivity list with wait usage
• Thinking <= operator is wrong here

5. You want to write a testbench to verify a VHDL design. Which construct is non-synthesizable but useful for simulation only?

hard

A. A clocked process with if rising_edge(clk) condition

B. A process with wait for 20 ns; to generate clock signals

C. Concurrent signal assignment for output signals

D. Signal assignment inside a synchronous reset process

Solution

1. Step 1: Identify testbench constructs

   Testbenches often use wait for statements to simulate timing delays, which are non-synthesizable.

2. Step 2: Compare with synthesizable constructs

   Options A, C, and D describe synthesizable hardware behavior, not simulation-only code.

3. Final Answer:

   A process with wait for 20 ns; to generate clock signals -> Option B

4. Quick Check:

   Wait for delays = simulation only [OK]

Hint: Use wait for delays only in testbenches, not hardware [OK]

Common Mistakes:

• Using wait for in synthesizable design code
• Confusing testbench and design code constructs
• Assuming clocked processes are non-synthesizable