Synthesizable vs non-synthesizable constructs in VHDL - Hands-On Comparison

Synthesizable vs Non-Synthesizable Constructs in VHDL

📖 Scenario: You are designing a simple digital circuit using VHDL. You need to understand which parts of your code can be turned into hardware (synthesizable) and which parts are only for simulation or testing (non-synthesizable).

🎯 Goal: Build a VHDL design that includes both synthesizable and non-synthesizable constructs. Learn to identify and separate them properly.

📋 What You'll Learn

Create a VHDL entity and architecture for a simple counter

Add a synthesizable process that increments the counter

Add a non-synthesizable process that prints the counter value for simulation

Display the counter value using a report statement in simulation

💡 Why This Matters

🌍 Real World

In real digital design projects, distinguishing synthesizable and non-synthesizable code helps ensure your design can be implemented on hardware and tested properly.

💼 Career

Understanding synthesizable vs non-synthesizable constructs is essential for FPGA and ASIC design engineers to write correct and efficient hardware description code.

1

Create a VHDL entity and architecture with a counter signal

Write a VHDL entity called Counter with a clock input clk of type std_logic. Inside the architecture, declare a signal called count of type integer initialized to 0.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity Counter is
    port (
        clk : in std_logic
    );
end Counter;

architecture Behavioral of Counter is
    signal count : integer := 0;
    -- Your code here
end Behavioral;

Hint

Remember to declare the entity with a clock input and a signal inside the architecture.

2

Add a synthesizable process to increment the counter on clock rising edge

Inside the architecture Behavioral, add a process named count_process that triggers on the rising edge of clk. Inside the process, increment the signal count by 1.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity Counter is
    port (
        clk : in std_logic
    );
end Counter;

architecture Behavioral of Counter is
    signal count : integer := 0;
begin
    -- Add a process named count_process that increments count on rising edge of clk
    -- Your code here
end Behavioral;

Hint

Use if rising_edge(clk) then inside the process to detect clock edges.

3

Add a non-synthesizable process to print the counter value for simulation

Add a process named print_process that triggers on the rising edge of clk. Inside this process, use the report statement to print the current value of count as a string. This process is for simulation only and is non-synthesizable.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Counter is
    port (
        clk : in std_logic
    );
end Counter;

architecture Behavioral of Counter is
    signal count : integer := 0;
begin
    count_process : process(clk)
    begin
        if rising_edge(clk) then
            count <= count + 1;
        end if;
    end process count_process;

    -- Add a process named print_process that reports count value on rising edge of clk
    -- Your code here
end Behavioral;

Hint

Use report with integer'image(count) to convert the integer to string for printing.

4

Simulate and observe the printed counter values

Run the VHDL simulation and observe the output messages printed by the print_process. The output should show the counter value increasing on each clock rising edge.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Counter is
    port (
        clk : in std_logic
    );
end Counter;

architecture Behavioral of Counter is
    signal count : integer := 0;
begin
    count_process : process(clk)
    begin
        if rising_edge(clk) then
            count <= count + 1;
        end if;
    end process count_process;

    print_process : process(clk)
    begin
        if rising_edge(clk) then
            report "Count value: " & integer'image(count);
        end if;
    end process print_process;

    -- Run simulation and observe output
    -- Your code here
end Behavioral;

Hint

Run your simulation tool and check the console or message window for the report outputs.

Practice

1. Which of the following VHDL constructs is synthesizable and can be implemented in hardware?

easy

A. Use of assert statements for debugging

B. A process containing wait for 10 ns; statements

C. File I/O operations like reading from a text file

D. A process with only clocked assignments and no wait statements

Solution

1. Step 1: Identify synthesizable constructs

   Synthesizable code must describe hardware behavior, typically using clocked processes without delays or waits.

2. Step 2: Analyze each option

   A process with only clocked assignments and no wait statements uses clocked assignments without waits, so it is synthesizable. Options A, B, and D use waits, assertions, or file I/O, which are non-synthesizable.

3. Final Answer:

   A process with only clocked assignments and no wait statements -> Option D

4. Quick Check:

   Synthesizable = clocked process without wait [OK]

Hint: Synthesizable means no waits or file I/O, just clocked logic [OK]

Common Mistakes:

• Thinking wait statements are synthesizable
• Confusing assert for hardware logic
• Assuming file I/O can be synthesized

2. Which VHDL syntax is not synthesizable?

easy

A. A process with a wait until clk = '1'; statement

B. Concurrent signal assignment outside any process

C. Signal assignment inside a clocked process

D. Using rising_edge(clk) inside a process

Solution

1. Step 1: Understand wait statement restrictions

   Wait statements like wait until clk = '1'; are not synthesizable because hardware cannot implement arbitrary waits.

2. Step 2: Check other options

   Options A, B, and C are standard synthesizable constructs: clock edge detection, signal assignments in processes, and concurrent assignments.

3. Final Answer:

   A process with a wait until clk = '1'; statement -> Option A

4. Quick Check:

   Wait statements = non-synthesizable [OK]

Hint: Wait statements inside processes are never synthesizable [OK]

Common Mistakes:

• Assuming wait until is synthesizable
• Confusing sensitivity list with wait statements
• Thinking concurrent assignments are non-synthesizable

3. What is the output behavior of this VHDL process when synthesized?

process(clk)
begin
  if rising_edge(clk) then
    if reset = '1' then
      q <= '0';
    else
      q <= d;
    end if;
  end if;
end process;

medium

A. q synchronously resets to '0' on clock edge when reset is '1'

B. q asynchronously resets to '0' when reset is '1'

C. q changes immediately when reset is '1', ignoring clock

D. q never resets because reset is ignored

Solution

1. Step 1: Analyze reset behavior inside clocked process

   The reset check is inside the rising_edge(clk) condition, so reset is synchronous.

2. Step 2: Understand output assignment timing

   q is assigned '0' only on clock edge when reset is '1', otherwise q follows d on clock edges.

3. Final Answer:

   q synchronously resets to '0' on clock edge when reset is '1' -> Option A

4. Quick Check:

   Synchronous reset inside clock edge = q synchronously resets to '0' on clock edge when reset is '1' [OK]

Hint: Reset inside rising_edge means synchronous reset [OK]

Common Mistakes:

• Thinking reset is asynchronous here
• Assuming q changes immediately without clock
• Ignoring the rising_edge condition

4. Identify the error in this VHDL code snippet that prevents synthesis:

process(clk)
begin
  wait until clk = '1';
  q <= d;
end process;

medium

A. Signal assignment outside process

B. Missing sensitivity list in process

C. Using wait statement inside a clocked process

D. Incorrect use of <= operator

Solution

1. Step 1: Check for wait statement usage

   Wait statements inside processes are not synthesizable and cause synthesis errors.

2. Step 2: Verify other syntax elements

   The process has a sensitivity list (clk), signal assignment is inside process, and <= is correctly used.

3. Final Answer:

   Using wait statement inside a clocked process -> Option C

4. Quick Check:

   Wait inside process = synthesis error [OK]

Hint: Wait statements inside processes cause synthesis errors [OK]

Common Mistakes:

• Ignoring that wait is not synthesizable
• Confusing sensitivity list with wait usage
• Thinking <= operator is wrong here

5. You want to write a testbench to verify a VHDL design. Which construct is non-synthesizable but useful for simulation only?

hard

A. A clocked process with if rising_edge(clk) condition

B. A process with wait for 20 ns; to generate clock signals

C. Concurrent signal assignment for output signals

D. Signal assignment inside a synchronous reset process

Solution

1. Step 1: Identify testbench constructs

   Testbenches often use wait for statements to simulate timing delays, which are non-synthesizable.

2. Step 2: Compare with synthesizable constructs

   Options A, C, and D describe synthesizable hardware behavior, not simulation-only code.

3. Final Answer:

   A process with wait for 20 ns; to generate clock signals -> Option B

4. Quick Check:

   Wait for delays = simulation only [OK]

Hint: Use wait for delays only in testbenches, not hardware [OK]

Common Mistakes:

• Using wait for in synthesizable design code
• Confusing testbench and design code constructs
• Assuming clocked processes are non-synthesizable