Synthesizable vs non-synthesizable constructs in VHDL - Practice Questions

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a process with wait statement

Consider the following VHDL process. What will be the output on signal out_signal after simulation?

VHDL

process
begin
  out_signal <= '1';
  wait for 10 ns;
  out_signal <= '0';
  wait;
end process;

A Signal <code>out_signal</code> first becomes '1' then after 10 ns becomes '0' and stays '0'.

B Signal <code>out_signal</code> stays '1' forever because wait statements are ignored in synthesis.

C Signal <code>out_signal</code> becomes '0' immediately without delay.

D The code will cause a synthesis error due to the wait statement.

💡 Hint

Think about how wait statements affect simulation and synthesis differently.

The wait statement pauses the process in simulation, so out_signal changes after 10 ns. This is valid for simulation but not synthesizable. However, the question asks about simulation output.

🧠 Conceptual

intermediate

Identifying synthesizable constructs

Which of the following VHDL constructs is synthesizable?

A A concurrent signal assignment with a conditional expression.

B A process containing a wait statement.

C A function that uses file I/O operations.

D A process with an infinite loop without any wait or sensitivity list.

💡 Hint

Synthesizable code must be implementable in hardware.

Concurrent signal assignments with conditions are synthesizable. Wait statements and file I/O are not synthesizable. Infinite loops without wait or sensitivity cause simulation hang and are not synthesizable.

🔧 Debug

advanced

Why does this VHDL code fail synthesis?

Given the following code snippet, why will synthesis tools reject it?

VHDL

process(clk)
begin
  if rising_edge(clk) then
    for i in 0 to 7 loop
      data_out(i) <= data_in(i) when enable = '1' else '0';
    end loop;
  end if;
end process;

A Because conditional signal assignments inside a for loop are not synthesizable.

B Because the for loop variable <code>i</code> is not declared.

C Because signal assignments inside a clocked process must not use conditional expressions.

D Because the conditional signal assignment syntax inside the loop is invalid.

💡 Hint

Check the syntax of the conditional assignment inside the loop.

The syntax signal <= value when condition else other_value; is a concurrent statement and cannot be used inside a sequential process. Inside a process, you must use if-else statements.

📝 Syntax

advanced

Which code snippet is synthesizable?

Which of the following VHDL code snippets is synthesizable?

A

process
begin
  q <= d;
  wait for 10 ns;
end process;

B

process
begin
  wait until clk = '1';
  q <= d;
end process;

C

process(clk)
begin
  if rising_edge(clk) then
    q <= d;
  end if;
end process;

D

process(clk)
begin
  if clk = '1' then
    q <= d;
  end if;
end process;

💡 Hint

Consider the correct way to write a clocked process for synthesis.

Option C uses the standard rising_edge(clk) check which is synthesizable. Option C uses wait until which is not synthesizable. Option C uses wait for which is not synthesizable. Option C uses a level check instead of edge detection, which is not recommended and may not synthesize correctly.

🚀 Application

expert

Determining synthesizable code from mixed constructs

Given the following VHDL code, how many signals will be correctly synthesized into hardware registers?

VHDL

signal a, b, c : std_logic;
process(clk)
begin
  if rising_edge(clk) then
    a <= b and c;
    wait for 5 ns;
    b <= a or c;
  end if;
end process;

A Both signals <code>a</code> and <code>b</code> will be synthesized as registers.

B No signals will be synthesized because of the wait statement inside the process.

C Only signal <code>a</code> will be synthesized as a register.

D Only signal <code>b</code> will be synthesized as a register.

💡 Hint

Wait statements inside clocked processes are not synthesizable.

The presence of a wait statement inside a clocked process makes the entire process non-synthesizable. Therefore, no registers will be created for signals a or b.

Practice

1. Which of the following VHDL constructs is synthesizable and can be implemented in hardware?

easy

A. Use of assert statements for debugging

B. A process containing wait for 10 ns; statements

C. File I/O operations like reading from a text file

D. A process with only clocked assignments and no wait statements

Solution

1. Step 1: Identify synthesizable constructs

   Synthesizable code must describe hardware behavior, typically using clocked processes without delays or waits.

2. Step 2: Analyze each option

   A process with only clocked assignments and no wait statements uses clocked assignments without waits, so it is synthesizable. Options A, B, and D use waits, assertions, or file I/O, which are non-synthesizable.

3. Final Answer:

   A process with only clocked assignments and no wait statements -> Option D

4. Quick Check:

   Synthesizable = clocked process without wait [OK]

Hint: Synthesizable means no waits or file I/O, just clocked logic [OK]

Common Mistakes:

• Thinking wait statements are synthesizable
• Confusing assert for hardware logic
• Assuming file I/O can be synthesized

2. Which VHDL syntax is not synthesizable?

easy

A. A process with a wait until clk = '1'; statement

B. Concurrent signal assignment outside any process

C. Signal assignment inside a clocked process

D. Using rising_edge(clk) inside a process

Solution

1. Step 1: Understand wait statement restrictions

   Wait statements like wait until clk = '1'; are not synthesizable because hardware cannot implement arbitrary waits.

2. Step 2: Check other options

   Options A, B, and C are standard synthesizable constructs: clock edge detection, signal assignments in processes, and concurrent assignments.

3. Final Answer:

   A process with a wait until clk = '1'; statement -> Option A

4. Quick Check:

   Wait statements = non-synthesizable [OK]

Hint: Wait statements inside processes are never synthesizable [OK]

Common Mistakes:

• Assuming wait until is synthesizable
• Confusing sensitivity list with wait statements
• Thinking concurrent assignments are non-synthesizable

3. What is the output behavior of this VHDL process when synthesized?

process(clk)
begin
  if rising_edge(clk) then
    if reset = '1' then
      q <= '0';
    else
      q <= d;
    end if;
  end if;
end process;

medium

A. q synchronously resets to '0' on clock edge when reset is '1'

B. q asynchronously resets to '0' when reset is '1'

C. q changes immediately when reset is '1', ignoring clock

D. q never resets because reset is ignored

Solution

1. Step 1: Analyze reset behavior inside clocked process

   The reset check is inside the rising_edge(clk) condition, so reset is synchronous.

2. Step 2: Understand output assignment timing

   q is assigned '0' only on clock edge when reset is '1', otherwise q follows d on clock edges.

3. Final Answer:

   q synchronously resets to '0' on clock edge when reset is '1' -> Option A

4. Quick Check:

   Synchronous reset inside clock edge = q synchronously resets to '0' on clock edge when reset is '1' [OK]

Hint: Reset inside rising_edge means synchronous reset [OK]

Common Mistakes:

• Thinking reset is asynchronous here
• Assuming q changes immediately without clock
• Ignoring the rising_edge condition

4. Identify the error in this VHDL code snippet that prevents synthesis:

process(clk)
begin
  wait until clk = '1';
  q <= d;
end process;

medium

A. Signal assignment outside process

B. Missing sensitivity list in process

C. Using wait statement inside a clocked process

D. Incorrect use of <= operator

Solution

1. Step 1: Check for wait statement usage

   Wait statements inside processes are not synthesizable and cause synthesis errors.

2. Step 2: Verify other syntax elements

   The process has a sensitivity list (clk), signal assignment is inside process, and <= is correctly used.

3. Final Answer:

   Using wait statement inside a clocked process -> Option C

4. Quick Check:

   Wait inside process = synthesis error [OK]

Hint: Wait statements inside processes cause synthesis errors [OK]

Common Mistakes:

• Ignoring that wait is not synthesizable
• Confusing sensitivity list with wait usage
• Thinking <= operator is wrong here

5. You want to write a testbench to verify a VHDL design. Which construct is non-synthesizable but useful for simulation only?

hard

A. A clocked process with if rising_edge(clk) condition

B. A process with wait for 20 ns; to generate clock signals

C. Concurrent signal assignment for output signals

D. Signal assignment inside a synchronous reset process

Solution

1. Step 1: Identify testbench constructs

   Testbenches often use wait for statements to simulate timing delays, which are non-synthesizable.

2. Step 2: Compare with synthesizable constructs

   Options A, C, and D describe synthesizable hardware behavior, not simulation-only code.

3. Final Answer:

   A process with wait for 20 ns; to generate clock signals -> Option B

4. Quick Check:

   Wait for delays = simulation only [OK]

Hint: Use wait for delays only in testbenches, not hardware [OK]

Common Mistakes:

• Using wait for in synthesizable design code
• Confusing testbench and design code constructs
• Assuming clocked processes are non-synthesizable