Synthesizable vs non-synthesizable constructs in VHDL - Quick Revision & Key Differences

Recall & Review

beginner

What does 'synthesizable' mean in VHDL?

Synthesizable means the VHDL code can be converted into actual hardware by synthesis tools.

beginner

Give an example of a non-synthesizable VHDL construct.

Using 'wait for' statements or file I/O operations are examples of non-synthesizable constructs.

intermediate

Why are some VHDL constructs non-synthesizable?

Because they describe behavior that cannot be directly mapped to hardware, like delays or file handling.

beginner

Is a process with only combinational logic synthesizable?

Yes, if it only uses logic operations and no timing or file operations, it is synthesizable.

intermediate

What happens if you use non-synthesizable constructs in code meant for FPGA synthesis?

The synthesis tool will give errors or ignore those parts, so the hardware won't behave as expected.

Which of these VHDL constructs is synthesizable?

A A process with only signal assignments and no delays

B A process with 'wait for 10 ns;' statement

C File reading operations

D Text output to console

Only processes with signal assignments and no timing or file operations are synthesizable.

Why can't 'wait for' statements be synthesized into hardware?

A They are only used for simulation

B They are too complex to understand

C They describe delays that hardware cannot implement directly

D They require software drivers

'wait for' describes delays which hardware cannot directly implement as a physical component.

Which is a characteristic of synthesizable VHDL code?

A Uses 'assert' statements for debugging

B Uses only constructs that map to hardware components

C Contains infinite loops without exit

D Includes file I/O operations

Synthesizable code must map to real hardware components.

What will synthesis tools do with non-synthesizable code?

A Optimize it automatically

B Convert it to hardware anyway

C Run it as software

D Report errors or ignore it

Synthesis tools cannot convert non-synthesizable code and will report errors or ignore it.

Which of these is synthesizable?

A A combinational logic process

B A process with 'wait until clk = '1''

C File write operations

D Text output commands

Combinational logic processes are synthesizable; timing waits and file operations are not.

Explain the difference between synthesizable and non-synthesizable VHDL constructs.

Think about what hardware can and cannot do.

List common non-synthesizable constructs in VHDL and why they are not synthesizable.

Consider what hardware components physically exist.

Practice

1. Which of the following VHDL constructs is synthesizable and can be implemented in hardware?

easy

A. Use of assert statements for debugging

B. A process containing wait for 10 ns; statements

C. File I/O operations like reading from a text file

D. A process with only clocked assignments and no wait statements

Solution

1. Step 1: Identify synthesizable constructs

   Synthesizable code must describe hardware behavior, typically using clocked processes without delays or waits.

2. Step 2: Analyze each option

   A process with only clocked assignments and no wait statements uses clocked assignments without waits, so it is synthesizable. Options A, B, and D use waits, assertions, or file I/O, which are non-synthesizable.

3. Final Answer:

   A process with only clocked assignments and no wait statements -> Option D

4. Quick Check:

   Synthesizable = clocked process without wait [OK]

Hint: Synthesizable means no waits or file I/O, just clocked logic [OK]

Common Mistakes:

• Thinking wait statements are synthesizable
• Confusing assert for hardware logic
• Assuming file I/O can be synthesized

2. Which VHDL syntax is not synthesizable?

easy

A. A process with a wait until clk = '1'; statement

B. Concurrent signal assignment outside any process

C. Signal assignment inside a clocked process

D. Using rising_edge(clk) inside a process

Solution

1. Step 1: Understand wait statement restrictions

   Wait statements like wait until clk = '1'; are not synthesizable because hardware cannot implement arbitrary waits.

2. Step 2: Check other options

   Options A, B, and C are standard synthesizable constructs: clock edge detection, signal assignments in processes, and concurrent assignments.

3. Final Answer:

   A process with a wait until clk = '1'; statement -> Option A

4. Quick Check:

   Wait statements = non-synthesizable [OK]

Hint: Wait statements inside processes are never synthesizable [OK]

Common Mistakes:

• Assuming wait until is synthesizable
• Confusing sensitivity list with wait statements
• Thinking concurrent assignments are non-synthesizable

3. What is the output behavior of this VHDL process when synthesized?

process(clk)
begin
  if rising_edge(clk) then
    if reset = '1' then
      q <= '0';
    else
      q <= d;
    end if;
  end if;
end process;

medium

A. q synchronously resets to '0' on clock edge when reset is '1'

B. q asynchronously resets to '0' when reset is '1'

C. q changes immediately when reset is '1', ignoring clock

D. q never resets because reset is ignored

Solution

1. Step 1: Analyze reset behavior inside clocked process

   The reset check is inside the rising_edge(clk) condition, so reset is synchronous.

2. Step 2: Understand output assignment timing

   q is assigned '0' only on clock edge when reset is '1', otherwise q follows d on clock edges.

3. Final Answer:

   q synchronously resets to '0' on clock edge when reset is '1' -> Option A

4. Quick Check:

   Synchronous reset inside clock edge = q synchronously resets to '0' on clock edge when reset is '1' [OK]

Hint: Reset inside rising_edge means synchronous reset [OK]

Common Mistakes:

• Thinking reset is asynchronous here
• Assuming q changes immediately without clock
• Ignoring the rising_edge condition

4. Identify the error in this VHDL code snippet that prevents synthesis:

process(clk)
begin
  wait until clk = '1';
  q <= d;
end process;

medium

A. Signal assignment outside process

B. Missing sensitivity list in process

C. Using wait statement inside a clocked process

D. Incorrect use of <= operator

Solution

1. Step 1: Check for wait statement usage

   Wait statements inside processes are not synthesizable and cause synthesis errors.

2. Step 2: Verify other syntax elements

   The process has a sensitivity list (clk), signal assignment is inside process, and <= is correctly used.

3. Final Answer:

   Using wait statement inside a clocked process -> Option C

4. Quick Check:

   Wait inside process = synthesis error [OK]

Hint: Wait statements inside processes cause synthesis errors [OK]

Common Mistakes:

• Ignoring that wait is not synthesizable
• Confusing sensitivity list with wait usage
• Thinking <= operator is wrong here

5. You want to write a testbench to verify a VHDL design. Which construct is non-synthesizable but useful for simulation only?

hard

A. A clocked process with if rising_edge(clk) condition

B. A process with wait for 20 ns; to generate clock signals

C. Concurrent signal assignment for output signals

D. Signal assignment inside a synchronous reset process

Solution

1. Step 1: Identify testbench constructs

   Testbenches often use wait for statements to simulate timing delays, which are non-synthesizable.

2. Step 2: Compare with synthesizable constructs

   Options A, C, and D describe synthesizable hardware behavior, not simulation-only code.

3. Final Answer:

   A process with wait for 20 ns; to generate clock signals -> Option B

4. Quick Check:

   Wait for delays = simulation only [OK]

Hint: Use wait for delays only in testbenches, not hardware [OK]

Common Mistakes:

• Using wait for in synthesizable design code
• Confusing testbench and design code constructs
• Assuming clocked processes are non-synthesizable