PWM generator in VHDL - Step-by-Step Execution

Concept Flow - PWM generator

Start

↓

Initialize counter = 0

↓

Increment counter

↓

Compare counter with duty_cycle

↓

counter < duty_cycle?

Yes→Output = '1'

↓

Output = '0'

↓

Reset counter if max reached

↓

Repeat

The PWM generator counts up each clock cycle, compares the count to the duty cycle, sets output high if count is less, else low, and resets the count after reaching max.

Execution Sample

VHDL

process(clk)
  begin
    if rising_edge(clk) then
      if counter < max_count then
        counter <= counter + 1;
      else
        counter <= 0;
      end if;
      pwm_out <= '1' when counter < duty_cycle else '0';
    end if;
  end process;

This code increments a counter each clock cycle, resets it at max_count, and sets pwm_out high if counter is less than duty_cycle.

Execution Table

Step	clk rising_edge?	counter before	counter after	counter < duty_cycle?	pwm_out
1	Yes	0	1	0 < 3 (True)	'1'
2	Yes	1	2	1 < 3 (True)	'1'
3	Yes	2	3	2 < 3 (True)	'1'
4	Yes	3	4	3 < 3 (False)	'0'
5	Yes	4	5	4 < 3 (False)	'0'
6	Yes	5	0	5 < 3 (False)	'0'
7	Yes	0	1	0 < 3 (True)	'1'

💡 Process repeats indefinitely on each rising clock edge.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7
counter	0	1	2	3	4	5	0	1
pwm_out	'1'	'1'	'1'	'1'	'0'	'0'	'0'	'1'

Key Moments - 2 Insights

Why does pwm_out become '0' when counter equals duty_cycle?

Because the condition is counter < duty_cycle, so when counter equals duty_cycle, the condition is false, setting pwm_out to '0' as shown in execution_table rows 4 and 5.

Why does the counter reset to 0 after reaching max_count?

To create a repeating PWM cycle, the counter resets after max_count (row 6), allowing the PWM signal to restart its pattern.

Visual Quiz - 3 Questions

Look at the execution table, what is pwm_out at step 4?

A '1'

B '0'

C Undefined

D 'Z'

💡 Hint

Check the 'pwm_out' column at step 4 in the execution_table.

At which step does the counter reset to 0?

A Step 6

B Step 3

C Step 5

D Step 7

💡 Hint

Look at the 'counter after' column to find when it goes back to 0.

If duty_cycle is increased to 5, what would pwm_out be at step 4?

A Undefined

B '0'

C '1'

D 'Z'

💡 Hint

Compare counter and duty_cycle at step 4 in the execution_table and variable_tracker.

Concept Snapshot

PWM Generator in VHDL:
- Use a counter incremented each clock rising edge.
- Compare counter with duty_cycle.
- Output '1' if counter < duty_cycle, else '0'.
- Reset counter after max_count to repeat cycle.
- Controls signal width by duty_cycle value.

Full Transcript

This visual execution shows a PWM generator in VHDL. The process triggers on each rising clock edge. The counter increments until it reaches max_count, then resets to zero. The output pwm_out is set to '1' when the counter is less than the duty_cycle, otherwise '0'. This creates a pulse width modulated signal where the high time depends on duty_cycle. The execution table traces each step, showing counter and output changes. Key moments clarify why output changes at certain counts and why the counter resets. The quiz tests understanding of output values and counter resets based on the visual trace.

Practice

1. What is the main purpose of a PWM generator in VHDL?

easy

A. To create a signal that switches on and off quickly to control power

B. To store data in memory

C. To perform arithmetic calculations

D. To generate random numbers

Solution

1. Step 1: Understand PWM function

   PWM (Pulse Width Modulation) generates a signal that switches on and off rapidly.

2. Step 2: Identify purpose in power control

   This switching controls the power delivered to devices by changing the duty cycle.

3. Final Answer:

   To create a signal that switches on and off quickly to control power -> Option A

4. Quick Check:

   PWM controls power by switching signal [OK]

Hint: PWM controls power by fast on/off switching [OK]

Common Mistakes:

• Confusing PWM with memory storage
• Thinking PWM does arithmetic
• Assuming PWM generates random signals

2. Which VHDL statement correctly compares a counter to a duty cycle to generate a PWM output?

easy

A. pwm_out := '1' if counter > duty_cycle else '0';

B. pwm_out = '1' when counter = duty_cycle else '0';

C. pwm_out <= '1' when counter < duty_cycle else '0';

D. pwm_out <= '1' if counter = duty_cycle else '0';

Solution

1. Step 1: Identify correct VHDL assignment syntax

   In VHDL, signal assignment uses '<=' and conditional assignment uses 'when ... else'.

2. Step 2: Match correct comparison and syntax

   pwm_out <= '1' when counter < duty_cycle else '0'; uses '<=' and 'when ... else' with correct comparison 'counter < duty_cycle'.

3. Final Answer:

   pwm_out <= '1' when counter < duty_cycle else '0'; -> Option C

4. Quick Check:

   VHDL signal conditional assignment = pwm_out <= '1' when counter < duty_cycle else '0'; [OK]

Hint: Use '<=' with 'when ... else' for conditional signal assignment [OK]

Common Mistakes:

• Using ':=' instead of '<=' for signals
• Using 'if' instead of 'when' in signal assignment
• Using '=' for assignment instead of comparison

3. Given this VHDL snippet for PWM output:

process(clk)
begin
  if rising_edge(clk) then
    if counter < duty_cycle then
      pwm_out <= '1';
    else
      pwm_out <= '0';
    end if;
    if counter = max_count then
      counter <= 0;
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

What is the value of pwm_out when counter is 3 and duty_cycle is 5?

medium

A. Undefined

B. '1'

C. '0'

D. Error

Solution

1. Step 1: Compare counter and duty_cycle values

   Counter is 3, duty_cycle is 5, so 3 < 5 is true.

2. Step 2: Determine pwm_out value based on condition

   Since counter < duty_cycle, pwm_out is assigned '1'.

3. Final Answer:

   '1' -> Option B

4. Quick Check:

   3 < 5 means pwm_out = '1' [OK]

Hint: If counter < duty_cycle, pwm_out is '1' [OK]

Common Mistakes:

• Confusing '<' with '>' in condition
• Assuming pwm_out is '0' when counter < duty_cycle
• Ignoring the process clock edge condition

4. Identify the error in this VHDL PWM process:

process(clk)
begin
  if clk'event and clk = '1' then
    if counter <= duty_cycle then
      pwm_out <= '1';
    else
      pwm_out <= '0';
    end if;
    if counter = max_count then
      counter <= 0;
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

medium

A. Using 'clk'event and clk = '1' instead of rising_edge(clk)

B. Using '<=' in 'if counter <= duty_cycle' instead of '<'

C. Missing reset condition for counter

D. No error, code is correct

Solution

1. Step 1: Check clock edge detection method

   Using 'clk'event and clk = '1' is legal but less safe than rising_edge(clk).

2. Step 2: Identify best practice for clock edge

   rising_edge(clk) is preferred for clarity and synthesis compatibility.

3. Final Answer:

   Using 'clk'event and clk = '1' instead of rising_edge(clk) -> Option A

4. Quick Check:

   Use rising_edge(clk) for clock detection [OK]

Hint: Use rising_edge(clk) for clock detection [OK]

Common Mistakes:

• Using 'clk'event and clk = '1' which is outdated
• Confusing '<=' with '<' in duty cycle comparison
• Ignoring reset logic necessity

5. You want to design a PWM generator in VHDL that supports variable frequency and duty cycle. Which approach correctly allows changing frequency and duty cycle dynamically?

hard

A. Use asynchronous signals to change frequency and duty cycle without counters

B. Use a fixed counter for frequency and hard-coded duty cycle value

C. Use a single counter and fix duty cycle at compile time

D. Use two counters: one for period (frequency) and one for duty cycle comparison, both updated dynamically

Solution

1. Step 1: Understand dynamic frequency and duty cycle needs

   Changing frequency means changing the PWM period, so a period counter is needed.

2. Step 2: Use counters for period and duty cycle comparison

   One counter tracks the period length, another compares to duty cycle to set output.

3. Step 3: Allow dynamic updates

   Both counters and duty cycle values must be variable to change PWM parameters on the fly.

4. Final Answer:

   Use two counters: one for period (frequency) and one for duty cycle comparison, both updated dynamically -> Option D

5. Quick Check:

   Two counters enable dynamic frequency and duty cycle [OK]

Hint: Use separate counters for period and duty cycle [OK]

Common Mistakes:

• Fixing duty cycle or frequency at compile time
• Using asynchronous signals causing glitches
• Trying to change frequency without a period counter