PWM generator in VHDL - Mini Project: Build & Apply

PWM generator

📖 Scenario: You want to create a simple Pulse Width Modulation (PWM) signal generator using VHDL. PWM signals are used in many electronics applications like controlling motor speed or LED brightness by changing the duty cycle of a square wave.

🎯 Goal: Build a VHDL module that generates a PWM signal with a fixed period and a configurable duty cycle.

📋 What You'll Learn

Create a counter to count clock cycles for one PWM period

Create a signal to hold the duty cycle value

Compare the counter with the duty cycle to generate the PWM output

Print the PWM output signal value in simulation

💡 Why This Matters

🌍 Real World

PWM signals are widely used in electronics to control devices like motors, LEDs, and power supplies by adjusting the power delivered without losing energy.

💼 Career

Understanding PWM generation in VHDL is important for FPGA and embedded systems engineers working on hardware control and digital design.

1

Create a clock counter for PWM period

Create a signal called counter of type integer range 0 to 9 initialized to 0. This will count clock cycles for one PWM period of 10 clock ticks.

VHDL

signal counter : integer range 0 to 9 := 0;  -- Your code here

Hint

Use signal counter : integer range 0 to 9 := 0; inside the architecture to create the counter.

2

Add a duty cycle signal

Add a signal called duty_cycle of type integer range 0 to 9 initialized to 5. This will hold the PWM duty cycle value.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity pwm_generator is
    port (
        clk : in std_logic;
        pwm_out : out std_logic
    );
end pwm_generator;

architecture Behavioral of pwm_generator is
    signal counter : integer range 0 to 9 := 0;
    signal duty_cycle : integer range 0 to 9 := 5;  -- Your code here
begin
    -- Your code here
end Behavioral;

Hint

Add signal duty_cycle : integer range 0 to 9 := 5; inside the architecture.

3

Implement the PWM counter and output logic

Inside the architecture, add a process triggered on the rising edge of clk. Increment counter by 1 each clock cycle. Reset counter to 0 when it reaches 9. Set pwm_out to '1' when counter < duty_cycle, else '0'.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity pwm_generator is
    port (
        clk : in std_logic;
        pwm_out : out std_logic
    );
end pwm_generator;

architecture Behavioral of pwm_generator is
    signal counter : integer range 0 to 9 := 0;
    signal duty_cycle : integer range 0 to 9 := 5;
begin
    process(clk)
    begin
        if rising_edge(clk) then
            -- Your code here
        end if;
    end process;
end Behavioral;

Hint

Use a process with if rising_edge(clk) to update counter. Use a conditional assignment for pwm_out.

4

Simulate and print PWM output

Add a testbench process that runs for 20 clock cycles. Toggle clk every 5 ns. Print the value of pwm_out each rising edge of clk using report statements.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity pwm_generator_tb is
end pwm_generator_tb;

architecture Behavioral of pwm_generator_tb is
    signal clk : std_logic := '0';
    signal pwm_out : std_logic;

    component pwm_generator
        port (
            clk : in std_logic;
            pwm_out : out std_logic
        );
    end component;

begin
    uut: pwm_generator port map(clk => clk, pwm_out => pwm_out);

    clk_process : process
    begin
        while now < 100 ns loop
            clk <= '0';
            wait for 5 ns;
            clk <= '1';
            wait for 5 ns;
            -- Your code here
        end loop;
        wait;
    end process;
end Behavioral;

Hint

Use a testbench process to toggle clk every 5 ns and use report to print pwm_out at each rising edge.

Practice

1. What is the main purpose of a PWM generator in VHDL?

easy

A. To create a signal that switches on and off quickly to control power

B. To store data in memory

C. To perform arithmetic calculations

D. To generate random numbers

Solution

1. Step 1: Understand PWM function

   PWM (Pulse Width Modulation) generates a signal that switches on and off rapidly.

2. Step 2: Identify purpose in power control

   This switching controls the power delivered to devices by changing the duty cycle.

3. Final Answer:

   To create a signal that switches on and off quickly to control power -> Option A

4. Quick Check:

   PWM controls power by switching signal [OK]

Hint: PWM controls power by fast on/off switching [OK]

Common Mistakes:

• Confusing PWM with memory storage
• Thinking PWM does arithmetic
• Assuming PWM generates random signals

2. Which VHDL statement correctly compares a counter to a duty cycle to generate a PWM output?

easy

A. pwm_out := '1' if counter > duty_cycle else '0';

B. pwm_out = '1' when counter = duty_cycle else '0';

C. pwm_out <= '1' when counter < duty_cycle else '0';

D. pwm_out <= '1' if counter = duty_cycle else '0';

Solution

1. Step 1: Identify correct VHDL assignment syntax

   In VHDL, signal assignment uses '<=' and conditional assignment uses 'when ... else'.

2. Step 2: Match correct comparison and syntax

   pwm_out <= '1' when counter < duty_cycle else '0'; uses '<=' and 'when ... else' with correct comparison 'counter < duty_cycle'.

3. Final Answer:

   pwm_out <= '1' when counter < duty_cycle else '0'; -> Option C

4. Quick Check:

   VHDL signal conditional assignment = pwm_out <= '1' when counter < duty_cycle else '0'; [OK]

Hint: Use '<=' with 'when ... else' for conditional signal assignment [OK]

Common Mistakes:

• Using ':=' instead of '<=' for signals
• Using 'if' instead of 'when' in signal assignment
• Using '=' for assignment instead of comparison

3. Given this VHDL snippet for PWM output:

process(clk)
begin
  if rising_edge(clk) then
    if counter < duty_cycle then
      pwm_out <= '1';
    else
      pwm_out <= '0';
    end if;
    if counter = max_count then
      counter <= 0;
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

What is the value of pwm_out when counter is 3 and duty_cycle is 5?

medium

A. Undefined

B. '1'

C. '0'

D. Error

Solution

1. Step 1: Compare counter and duty_cycle values

   Counter is 3, duty_cycle is 5, so 3 < 5 is true.

2. Step 2: Determine pwm_out value based on condition

   Since counter < duty_cycle, pwm_out is assigned '1'.

3. Final Answer:

   '1' -> Option B

4. Quick Check:

   3 < 5 means pwm_out = '1' [OK]

Hint: If counter < duty_cycle, pwm_out is '1' [OK]

Common Mistakes:

• Confusing '<' with '>' in condition
• Assuming pwm_out is '0' when counter < duty_cycle
• Ignoring the process clock edge condition

4. Identify the error in this VHDL PWM process:

process(clk)
begin
  if clk'event and clk = '1' then
    if counter <= duty_cycle then
      pwm_out <= '1';
    else
      pwm_out <= '0';
    end if;
    if counter = max_count then
      counter <= 0;
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

medium

A. Using 'clk'event and clk = '1' instead of rising_edge(clk)

B. Using '<=' in 'if counter <= duty_cycle' instead of '<'

C. Missing reset condition for counter

D. No error, code is correct

Solution

1. Step 1: Check clock edge detection method

   Using 'clk'event and clk = '1' is legal but less safe than rising_edge(clk).

2. Step 2: Identify best practice for clock edge

   rising_edge(clk) is preferred for clarity and synthesis compatibility.

3. Final Answer:

   Using 'clk'event and clk = '1' instead of rising_edge(clk) -> Option A

4. Quick Check:

   Use rising_edge(clk) for clock detection [OK]

Hint: Use rising_edge(clk) for clock detection [OK]

Common Mistakes:

• Using 'clk'event and clk = '1' which is outdated
• Confusing '<=' with '<' in duty cycle comparison
• Ignoring reset logic necessity

5. You want to design a PWM generator in VHDL that supports variable frequency and duty cycle. Which approach correctly allows changing frequency and duty cycle dynamically?

hard

A. Use asynchronous signals to change frequency and duty cycle without counters

B. Use a fixed counter for frequency and hard-coded duty cycle value

C. Use a single counter and fix duty cycle at compile time

D. Use two counters: one for period (frequency) and one for duty cycle comparison, both updated dynamically

Solution

1. Step 1: Understand dynamic frequency and duty cycle needs

   Changing frequency means changing the PWM period, so a period counter is needed.

2. Step 2: Use counters for period and duty cycle comparison

   One counter tracks the period length, another compares to duty cycle to set output.

3. Step 3: Allow dynamic updates

   Both counters and duty cycle values must be variable to change PWM parameters on the fly.

4. Final Answer:

   Use two counters: one for period (frequency) and one for duty cycle comparison, both updated dynamically -> Option D

5. Quick Check:

   Two counters enable dynamic frequency and duty cycle [OK]

Hint: Use separate counters for period and duty cycle [OK]

Common Mistakes:

• Fixing duty cycle or frequency at compile time
• Using asynchronous signals causing glitches
• Trying to change frequency without a period counter