PWM generator in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a signal named duty_cycle of type unsigned with 8 bits.

VHDL

signal duty_cycle : [1](7 downto 0);

Drag options to blanks, or click blank then click option'

Aunsigned

Binteger

Cstd_logic_vector

Dbit_vector

Attempts:

3 left

💡 Hint

Common Mistakes

Using std_logic_vector instead of unsigned for duty_cycle.

Declaring duty_cycle as integer without range.

The duty_cycle signal should be declared as unsigned to represent numeric values for PWM width.

2fill in blank

medium

Complete the process sensitivity list to trigger on clock and reset signals.

VHDL

process([1])
begin
  -- process body
end process;

Drag options to blanks, or click blank then click option'

Aclk, reset

Bclk

Creset

Dclk or reset

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'or' instead of ',' in sensitivity list.

Including only one signal in sensitivity list.

The sensitivity list should include both clk and reset separated by , to react to changes on either signal.

3fill in blank

hard

Fix the error in the if statement checking for rising edge of clock.

VHDL

if [1](clk) then
  -- code
end if;

Drag options to blanks, or click blank then click option'

Aposedge

Bfalling_edge

Crising_edge

Dposedge_edge

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'posedge' which is Verilog syntax, not VHDL.

Using 'falling_edge' when rising edge is needed.

The correct VHDL function to detect a rising edge is rising_edge(clk).

4fill in blank

hard

Fill both blanks to compare counter with duty_cycle and assign PWM output.

VHDL

if counter [1] duty_cycle then
  pwm_out <= '[2]';
else
  pwm_out <= '0';
end if;

Drag options to blanks, or click blank then click option'

A<

B'1'

C'0'

D<=

Attempts:

3 left

💡 Hint

Common Mistakes

Using '<=' instead of '<' causes off-by-one error.

Assigning '0' instead of '1' when condition is true.

The PWM output is high ('1') when the counter is less than the duty cycle.

5fill in blank

hard

Fill all three blanks to complete the process sensitivity list and counter increment for PWM generator.

VHDL

process([1], [2])
begin
  if rising_edge(clk) then
    if reset = '1' then
      counter <= (others => '0');
    else
      counter <= counter [3] 1;
    end if;
  end if;
end process;

Drag options to blanks, or click blank then click option'

Aclk

Breset

C+

D-

Attempts:

3 left

💡 Hint

Common Mistakes

Using '-' instead of '+' for increment.

Missing reset signal in sensitivity list.

The process is sensitive to clock and reset. On reset, counter resets to zero. Otherwise, it increments by 1.

Practice

1. What is the main purpose of a PWM generator in VHDL?

easy

A. To create a signal that switches on and off quickly to control power

B. To store data in memory

C. To perform arithmetic calculations

D. To generate random numbers

Solution

1. Step 1: Understand PWM function

   PWM (Pulse Width Modulation) generates a signal that switches on and off rapidly.

2. Step 2: Identify purpose in power control

   This switching controls the power delivered to devices by changing the duty cycle.

3. Final Answer:

   To create a signal that switches on and off quickly to control power -> Option A

4. Quick Check:

   PWM controls power by switching signal [OK]

Hint: PWM controls power by fast on/off switching [OK]

Common Mistakes:

• Confusing PWM with memory storage
• Thinking PWM does arithmetic
• Assuming PWM generates random signals

2. Which VHDL statement correctly compares a counter to a duty cycle to generate a PWM output?

easy

A. pwm_out := '1' if counter > duty_cycle else '0';

B. pwm_out = '1' when counter = duty_cycle else '0';

C. pwm_out <= '1' when counter < duty_cycle else '0';

D. pwm_out <= '1' if counter = duty_cycle else '0';

Solution

1. Step 1: Identify correct VHDL assignment syntax

   In VHDL, signal assignment uses '<=' and conditional assignment uses 'when ... else'.

2. Step 2: Match correct comparison and syntax

   pwm_out <= '1' when counter < duty_cycle else '0'; uses '<=' and 'when ... else' with correct comparison 'counter < duty_cycle'.

3. Final Answer:

   pwm_out <= '1' when counter < duty_cycle else '0'; -> Option C

4. Quick Check:

   VHDL signal conditional assignment = pwm_out <= '1' when counter < duty_cycle else '0'; [OK]

Hint: Use '<=' with 'when ... else' for conditional signal assignment [OK]

Common Mistakes:

• Using ':=' instead of '<=' for signals
• Using 'if' instead of 'when' in signal assignment
• Using '=' for assignment instead of comparison

3. Given this VHDL snippet for PWM output:

process(clk)
begin
  if rising_edge(clk) then
    if counter < duty_cycle then
      pwm_out <= '1';
    else
      pwm_out <= '0';
    end if;
    if counter = max_count then
      counter <= 0;
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

What is the value of pwm_out when counter is 3 and duty_cycle is 5?

medium

A. Undefined

B. '1'

C. '0'

D. Error

Solution

1. Step 1: Compare counter and duty_cycle values

   Counter is 3, duty_cycle is 5, so 3 < 5 is true.

2. Step 2: Determine pwm_out value based on condition

   Since counter < duty_cycle, pwm_out is assigned '1'.

3. Final Answer:

   '1' -> Option B

4. Quick Check:

   3 < 5 means pwm_out = '1' [OK]

Hint: If counter < duty_cycle, pwm_out is '1' [OK]

Common Mistakes:

• Confusing '<' with '>' in condition
• Assuming pwm_out is '0' when counter < duty_cycle
• Ignoring the process clock edge condition

4. Identify the error in this VHDL PWM process:

process(clk)
begin
  if clk'event and clk = '1' then
    if counter <= duty_cycle then
      pwm_out <= '1';
    else
      pwm_out <= '0';
    end if;
    if counter = max_count then
      counter <= 0;
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

medium

A. Using 'clk'event and clk = '1' instead of rising_edge(clk)

B. Using '<=' in 'if counter <= duty_cycle' instead of '<'

C. Missing reset condition for counter

D. No error, code is correct

Solution

1. Step 1: Check clock edge detection method

   Using 'clk'event and clk = '1' is legal but less safe than rising_edge(clk).

2. Step 2: Identify best practice for clock edge

   rising_edge(clk) is preferred for clarity and synthesis compatibility.

3. Final Answer:

   Using 'clk'event and clk = '1' instead of rising_edge(clk) -> Option A

4. Quick Check:

   Use rising_edge(clk) for clock detection [OK]

Hint: Use rising_edge(clk) for clock detection [OK]

Common Mistakes:

• Using 'clk'event and clk = '1' which is outdated
• Confusing '<=' with '<' in duty cycle comparison
• Ignoring reset logic necessity

5. You want to design a PWM generator in VHDL that supports variable frequency and duty cycle. Which approach correctly allows changing frequency and duty cycle dynamically?

hard

A. Use asynchronous signals to change frequency and duty cycle without counters

B. Use a fixed counter for frequency and hard-coded duty cycle value

C. Use a single counter and fix duty cycle at compile time

D. Use two counters: one for period (frequency) and one for duty cycle comparison, both updated dynamically

Solution

1. Step 1: Understand dynamic frequency and duty cycle needs

   Changing frequency means changing the PWM period, so a period counter is needed.

2. Step 2: Use counters for period and duty cycle comparison

   One counter tracks the period length, another compares to duty cycle to set output.

3. Step 3: Allow dynamic updates

   Both counters and duty cycle values must be variable to change PWM parameters on the fly.

4. Final Answer:

   Use two counters: one for period (frequency) and one for duty cycle comparison, both updated dynamically -> Option D

5. Quick Check:

   Two counters enable dynamic frequency and duty cycle [OK]

Hint: Use separate counters for period and duty cycle [OK]

Common Mistakes:

• Fixing duty cycle or frequency at compile time
• Using asynchronous signals causing glitches
• Trying to change frequency without a period counter