PWM generator in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output waveform duty cycle?

Given this VHDL PWM process, what is the duty cycle of the output signal pwm_out?

VHDL

process(clk)
  variable counter : integer range 0 to 9 := 0;
begin
  if rising_edge(clk) then
    if counter < 9 then
      counter := counter + 1;
    else
      counter := 0;
    end if;
    if counter < 3 then
      pwm_out <= '1';
    else
      pwm_out <= '0';
    end if;
  end if;
end process;

A 90%

B 70%

C 50%

D 30%

💡 Hint

Count how many clock cycles pwm_out stays high in one full cycle.

The counter counts from 0 to 9 (10 cycles). The output is '1' when counter is less than 3, so 3 cycles high out of 10 total cycles. Duty cycle = 3/10 = 30%.

❓ Predict Output

intermediate

What is the frequency of the PWM output if clk is 50 MHz?

Given the same PWM process as before, what is the frequency of the PWM output signal pwm_out if the input clock clk runs at 50 MHz?

VHDL

process(clk)
  variable counter : integer range 0 to 9 := 0;
begin
  if rising_edge(clk) then
    if counter < 9 then
      counter := counter + 1;
    else
      counter := 0;
    end if;
    if counter < 3 then
      pwm_out <= '1';
    else
      pwm_out <= '0';
    end if;
  end if;
end process;

A 500 kHz

B 5 MHz

C 50 MHz

D 10 MHz

💡 Hint

Calculate the PWM period in clock cycles and convert to frequency.

The counter counts 10 clock cycles per PWM period. Clock frequency is 50 MHz, so PWM frequency = 50 MHz / 10 = 5 MHz.

🔧 Debug

advanced

Identify the error in this PWM process

What error will this VHDL code cause when synthesizing a PWM generator?

VHDL

process(clk)
  variable counter : integer range 0 to 9 := 0;
begin
  if rising_edge(clk) then
    if counter <= 9 then
      counter := counter + 1;
    else
      counter := 0;
    end if;
    if counter < 3 then
      pwm_out <= '1';
    else
      pwm_out <= '0';
    end if;
  end if;
end process;

A Counter will increment to 10 causing range violation

B Counter will never reset, causing infinite count

C Counter will increment beyond range causing runtime error

D Counter will overflow causing synthesis error

💡 Hint

Check the condition that increments the counter and the variable range.

The counter variable is declared with range 0 to 9. The condition if counter <= 9 then counter := counter + 1; allows counter to increment to 10, which is outside the declared range, causing a range violation error.

📝 Syntax

advanced

Which option fixes the syntax error in this PWM code?

Find the option that corrects the syntax error in this PWM process code snippet.

VHDL

process(clk)
  variable counter : integer range 0 to 9 := 0;
begin
  if rising_edge(clk) then
    if counter < 9 then
      counter := counter + 1;
    else
      counter := 0;
    end if;
    if counter < 3 then
      pwm_out <= '1';
    else
      pwm_out <= '0';
    end if;
  end if;
end process;

A Remove the 'begin' keyword

B Replace 'variable' with 'signal' keyword

C Add a semicolon after variable declaration line

D Change 'if rising_edge(clk)' to 'if clk' condition

💡 Hint

Check the line before begin for missing punctuation.

In VHDL, variable declarations must end with a semicolon. The line variable counter : integer range 0 to 9 := 0 is missing a semicolon.

🚀 Application

expert

Calculate PWM output high time in nanoseconds

Given a PWM generator with a 100 MHz clock and a counter range of 0 to 19, where the output is high when counter < 5, what is the high time of the PWM output in nanoseconds?

VHDL

process(clk)
  variable counter : integer range 0 to 19 := 0;
begin
  if rising_edge(clk) then
    if counter < 19 then
      counter := counter + 1;
    else
      counter := 0;
    end if;
    if counter < 5 then
      pwm_out <= '1';
    else
      pwm_out <= '0';
    end if;
  end if;
end process;

A 50 ns

B 5 ns

C 20 ns

D 100 ns

💡 Hint

Calculate clock period and multiply by number of high cycles.

Clock frequency is 100 MHz, so clock period = 1 / 100 MHz = 10 ns. Output is high for 5 cycles, so high time = 5 * 10 ns = 50 ns.

Practice

1. What is the main purpose of a PWM generator in VHDL?

easy

A. To create a signal that switches on and off quickly to control power

B. To store data in memory

C. To perform arithmetic calculations

D. To generate random numbers

Solution

1. Step 1: Understand PWM function

   PWM (Pulse Width Modulation) generates a signal that switches on and off rapidly.

2. Step 2: Identify purpose in power control

   This switching controls the power delivered to devices by changing the duty cycle.

3. Final Answer:

   To create a signal that switches on and off quickly to control power -> Option A

4. Quick Check:

   PWM controls power by switching signal [OK]

Hint: PWM controls power by fast on/off switching [OK]

Common Mistakes:

• Confusing PWM with memory storage
• Thinking PWM does arithmetic
• Assuming PWM generates random signals

2. Which VHDL statement correctly compares a counter to a duty cycle to generate a PWM output?

easy

A. pwm_out := '1' if counter > duty_cycle else '0';

B. pwm_out = '1' when counter = duty_cycle else '0';

C. pwm_out <= '1' when counter < duty_cycle else '0';

D. pwm_out <= '1' if counter = duty_cycle else '0';

Solution

1. Step 1: Identify correct VHDL assignment syntax

   In VHDL, signal assignment uses '<=' and conditional assignment uses 'when ... else'.

2. Step 2: Match correct comparison and syntax

   pwm_out <= '1' when counter < duty_cycle else '0'; uses '<=' and 'when ... else' with correct comparison 'counter < duty_cycle'.

3. Final Answer:

   pwm_out <= '1' when counter < duty_cycle else '0'; -> Option C

4. Quick Check:

   VHDL signal conditional assignment = pwm_out <= '1' when counter < duty_cycle else '0'; [OK]

Hint: Use '<=' with 'when ... else' for conditional signal assignment [OK]

Common Mistakes:

• Using ':=' instead of '<=' for signals
• Using 'if' instead of 'when' in signal assignment
• Using '=' for assignment instead of comparison

3. Given this VHDL snippet for PWM output:

process(clk)
begin
  if rising_edge(clk) then
    if counter < duty_cycle then
      pwm_out <= '1';
    else
      pwm_out <= '0';
    end if;
    if counter = max_count then
      counter <= 0;
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

What is the value of pwm_out when counter is 3 and duty_cycle is 5?

medium

A. Undefined

B. '1'

C. '0'

D. Error

Solution

1. Step 1: Compare counter and duty_cycle values

   Counter is 3, duty_cycle is 5, so 3 < 5 is true.

2. Step 2: Determine pwm_out value based on condition

   Since counter < duty_cycle, pwm_out is assigned '1'.

3. Final Answer:

   '1' -> Option B

4. Quick Check:

   3 < 5 means pwm_out = '1' [OK]

Hint: If counter < duty_cycle, pwm_out is '1' [OK]

Common Mistakes:

• Confusing '<' with '>' in condition
• Assuming pwm_out is '0' when counter < duty_cycle
• Ignoring the process clock edge condition

4. Identify the error in this VHDL PWM process:

process(clk)
begin
  if clk'event and clk = '1' then
    if counter <= duty_cycle then
      pwm_out <= '1';
    else
      pwm_out <= '0';
    end if;
    if counter = max_count then
      counter <= 0;
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

medium

A. Using 'clk'event and clk = '1' instead of rising_edge(clk)

B. Using '<=' in 'if counter <= duty_cycle' instead of '<'

C. Missing reset condition for counter

D. No error, code is correct

Solution

1. Step 1: Check clock edge detection method

   Using 'clk'event and clk = '1' is legal but less safe than rising_edge(clk).

2. Step 2: Identify best practice for clock edge

   rising_edge(clk) is preferred for clarity and synthesis compatibility.

3. Final Answer:

   Using 'clk'event and clk = '1' instead of rising_edge(clk) -> Option A

4. Quick Check:

   Use rising_edge(clk) for clock detection [OK]

Hint: Use rising_edge(clk) for clock detection [OK]

Common Mistakes:

• Using 'clk'event and clk = '1' which is outdated
• Confusing '<=' with '<' in duty cycle comparison
• Ignoring reset logic necessity

5. You want to design a PWM generator in VHDL that supports variable frequency and duty cycle. Which approach correctly allows changing frequency and duty cycle dynamically?

hard

A. Use asynchronous signals to change frequency and duty cycle without counters

B. Use a fixed counter for frequency and hard-coded duty cycle value

C. Use a single counter and fix duty cycle at compile time

D. Use two counters: one for period (frequency) and one for duty cycle comparison, both updated dynamically

Solution

1. Step 1: Understand dynamic frequency and duty cycle needs

   Changing frequency means changing the PWM period, so a period counter is needed.

2. Step 2: Use counters for period and duty cycle comparison

   One counter tracks the period length, another compares to duty cycle to set output.

3. Step 3: Allow dynamic updates

   Both counters and duty cycle values must be variable to change PWM parameters on the fly.

4. Final Answer:

   Use two counters: one for period (frequency) and one for duty cycle comparison, both updated dynamically -> Option D

5. Quick Check:

   Two counters enable dynamic frequency and duty cycle [OK]

Hint: Use separate counters for period and duty cycle [OK]

Common Mistakes:

• Fixing duty cycle or frequency at compile time
• Using asynchronous signals causing glitches
• Trying to change frequency without a period counter