Why Procedure declaration and usage in VHDL? - Purpose & Use Cases

The Big Idea

What if you could fix a bug in one place and instantly improve your whole VHDL design?

The Scenario

Imagine you have to repeat the same set of instructions many times in your VHDL code, like turning on a light, waiting, then turning it off. You write the same lines over and over in different places.

The Problem

This manual way is slow and boring. If you want to change the instructions, you must find and edit every copy. It's easy to make mistakes or forget one place, causing bugs that are hard to find.

The Solution

With procedure declaration and usage, you write the instructions once as a procedure. Then, you just call that procedure whenever you need it. This keeps your code clean, easy to read, and simple to update.

Before vs After

✗ Before

signal light : std_logic;
-- Turn on light
light <= '1';
wait for 10 ns;
-- Turn off light
light <= '0';

✓ After

procedure toggle_light is
begin
  light <= '1';
  wait for 10 ns;
  light <= '0';
end procedure toggle_light;

-- Call procedure
toggle_light;

What It Enables

You can build complex VHDL designs faster and with fewer errors by reusing clear, tested blocks of code.

Real Life Example

Think of a factory machine that needs the same start-up steps every time it runs. Instead of writing those steps repeatedly, you create a procedure for start-up and call it whenever the machine starts.

Key Takeaways

Procedures let you write repeated instructions once and reuse them.

This saves time and reduces mistakes in your VHDL code.

It makes your designs easier to read and maintain.

Practice

1. What is the main purpose of a procedure in VHDL?

easy

A. To group a set of instructions for reuse

B. To declare a new signal

C. To define a new entity

D. To assign values to constants

Solution

1. Step 1: Understand what a procedure does

   A procedure groups instructions to perform a specific task that can be reused multiple times in the code.

2. Step 2: Compare with other options

   Declaring signals, entities, or assigning constants are different VHDL tasks, not the main purpose of procedures.

3. Final Answer:

   To group a set of instructions for reuse -> Option A

4. Quick Check:

   Procedure = reusable instruction group [OK]

Hint: Procedures bundle instructions for reuse [OK]

Common Mistakes:

• Confusing procedures with signal declarations
• Thinking procedures define entities
• Assuming procedures assign constants

2. Which of the following is the correct way to declare a procedure in VHDL?

easy

A. procedure my_proc() begin
-- code
end procedure;

B. procedure my_proc is
begin
-- code
end procedure;

C. procedure my_proc is
-- code
end;

D. procedure my_proc is
begin
-- code
end;

Solution

1. Step 1: Recall VHDL procedure syntax

   A procedure declaration uses the syntax: procedure name is begin ... end procedure;.

2. Step 2: Check each option

   procedure my_proc is begin -- code end procedure; matches the correct syntax with is, begin, and end procedure;. Options B, C, and D have syntax errors or missing keywords.

3. Final Answer:

   procedure my_proc is begin -- code end procedure; -> Option B

4. Quick Check:

   Procedure syntax = procedure my_proc is begin -- code end procedure; [OK]

Hint: Procedure ends with 'end procedure;' [OK]

Common Mistakes:

• Omitting 'procedure' keyword at the end
• Using parentheses after procedure name
• Ending with just 'end;' instead of 'end procedure;'

3. What will be the output of the following VHDL procedure call?

procedure add_one(signal x : inout integer) is
begin
  x <= x + 1;
end procedure;

signal val : integer := 5;
begin
  add_one(val);
  -- What is val now?
end;

medium

A. 5

B. 7

C. 6

D. Error: procedure call syntax

Solution

1. Step 1: Understand procedure behavior

   The procedure add_one takes a signal x as inout and increments it by 1.

2. Step 2: Apply procedure to signal val

   Initially, val is 5. After calling add_one(val);, val becomes 5 + 1 = 6.

3. Final Answer:

   6 -> Option C

4. Quick Check:

   5 + 1 = 6 [OK]

Hint: Inout parameter changes value inside procedure [OK]

Common Mistakes:

• Assuming input parameters cannot change
• Confusing procedure call syntax
• Forgetting procedure modifies signal

4. Identify the error in this procedure declaration:

procedure multiply_by_two(x : in integer; y : out integer) is
begin
  y := x * 2;
end;

medium

A. Procedure must end with 'end procedure;' not just 'end;'

B. Procedure body cannot assign values to 'out' parameters

C. Parameters cannot have modes like 'in' or 'out'

D. Missing 'procedure' keyword before 'multiply_by_two'

Solution

1. Step 1: Check procedure ending syntax

   In VHDL, a procedure must end with end procedure; not just end;.

2. Step 2: Verify other parts

   The procedure keyword is present, parameter modes are allowed, and assigning to 'out' parameters is valid.

3. Final Answer:

   Procedure must end with 'end procedure;' not just 'end;' -> Option A

4. Quick Check:

   Procedure ends with 'end procedure;' [OK]

Hint: Procedure must end with 'end procedure;' [OK]

Common Mistakes:

• Ending procedure with just 'end;'
• Thinking parameter modes are not allowed
• Confusing procedure and function endings

5. You want to create a procedure that swaps two integer signals a and b. Which of the following is the correct procedure declaration and usage?

hard

A. procedure swap(signal x, y : in integer) is
variable temp : integer;
begin
temp := x;
x := y;
y := temp;
end procedure;

-- Usage: swap(a, b);

B. procedure swap(signal x, y : out integer) is
variable temp : integer;
begin
temp := x;
x := y;
y := temp;
end procedure;

-- Usage: swap(a, b);

C. procedure swap(x, y : integer) is
variable temp : integer;
begin
temp := x;
x := y;
y := temp;
end procedure;

-- Usage: swap(a, b);

D. procedure swap(signal x, y : inout integer) is
variable temp : integer;
begin
temp := x;
x <= y;
y <= temp;
end procedure;

-- Usage: swap(a, b);

Solution

1. Step 1: Determine correct parameter modes for swapping

   To swap values, both parameters must be inout or signal with mode allowing read and write. 'inout' is correct.

2. Step 2: Check procedure declaration and usage

   procedure swap(signal x, y : inout integer) is variable temp : integer; begin temp := x; x <= y; y <= temp; end procedure; -- Usage: swap(a, b); declares parameters as signal x, y : inout integer and uses a temporary variable to swap values correctly. Usage is correct.

3. Final Answer:

   procedure swap(signal x, y : inout integer) is variable temp : integer; begin temp := x; x <= y; y <= temp; end procedure; -- Usage: swap(a, b); -> Option D

4. Quick Check:

   Swap needs inout parameters [OK]

Hint: Use 'inout' mode to modify both parameters [OK]

Common Mistakes:

• Using 'in' mode which is read-only
• Using 'out' mode which cannot read input
• Omitting 'signal' keyword for signals