Procedure declaration and usage in VHDL - Mini Project: Build & Apply

Procedure declaration and usage in VHDL

📖 Scenario: You are designing a simple VHDL module that needs to perform a repeated task of adding two numbers. Instead of writing the addition logic multiple times, you will create a procedure to do this addition and then use it in your design.

🎯 Goal: Create a VHDL procedure called add_numbers that takes two input integers and returns their sum through an output parameter. Then, use this procedure inside a process to add two numbers and display the result.

📋 What You'll Learn

Declare a procedure named add_numbers with two input parameters a and b of type integer and one output parameter result of type integer.

Inside the procedure, assign the sum of a and b to result.

Create a signal sum_result of type integer to hold the output of the procedure.

Call the procedure add_numbers inside a process to add two numbers, for example 5 and 7.

Use report statement to display the value of sum_result.

💡 Why This Matters

🌍 Real World

Procedures help reuse code in hardware designs, making them cleaner and easier to maintain.

💼 Career

Knowing how to write and use procedures is important for FPGA and ASIC designers to create modular and efficient VHDL code.

1

Declare the procedure add_numbers

Write a VHDL procedure named add_numbers that has two input parameters a and b of type integer and one output parameter result of type integer. Inside the procedure, assign result := a + b;.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity adder is
end entity;

architecture behavior of adder is

-- Declare procedure add_numbers here

begin

end behavior;

Hint

Remember, a procedure in VHDL is declared inside the architecture before the begin keyword.

2

Create a signal sum_result to hold the output

Inside the architecture declaration, create a signal named sum_result of type integer to store the result of the addition.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity adder is
end entity;

architecture behavior of adder is

  procedure add_numbers(a : in integer; b : in integer; result : out integer) is
  begin
    result := a + b;
  end procedure;

  -- Declare signal sum_result here

begin

end behavior;

Hint

Signals are declared inside the architecture but before the begin keyword.

3

Call the procedure inside a process to add 5 and 7

Add a process inside the architecture body. Inside the process, call the procedure add_numbers with inputs 5 and 7, and output sum_result.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity adder is
end entity;

architecture behavior of adder is

  procedure add_numbers(a : in integer; b : in integer; result : out integer) is
  begin
    result := a + b;
  end procedure;

  signal sum_result : integer := 0;

begin
  -- Add a process here to call add_numbers with 5 and 7

end behavior;

Hint

Use a simple process with no sensitivity list and a wait; statement to run once.

4

Display the result using a report statement

Inside the process, after calling add_numbers, add a report statement to display the text "Sum is: " followed by the value of sum_result. Use integer'image(sum_result) to convert the integer to string.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity adder is
end entity;

architecture behavior of adder is

  procedure add_numbers(a : in integer; b : in integer; result : out integer) is
  begin
    result := a + b;
  end procedure;

  signal sum_result : integer := 0;

begin
  process
  begin
    add_numbers(5, 7, sum_result);
    -- Add report statement here to display sum_result
    wait;
  end process;
end behavior;

Hint

The report statement prints messages during simulation. Use integer'image to convert integers to strings.

Practice

1. What is the main purpose of a procedure in VHDL?

easy

A. To group a set of instructions for reuse

B. To declare a new signal

C. To define a new entity

D. To assign values to constants

Solution

1. Step 1: Understand what a procedure does

   A procedure groups instructions to perform a specific task that can be reused multiple times in the code.

2. Step 2: Compare with other options

   Declaring signals, entities, or assigning constants are different VHDL tasks, not the main purpose of procedures.

3. Final Answer:

   To group a set of instructions for reuse -> Option A

4. Quick Check:

   Procedure = reusable instruction group [OK]

Hint: Procedures bundle instructions for reuse [OK]

Common Mistakes:

• Confusing procedures with signal declarations
• Thinking procedures define entities
• Assuming procedures assign constants

2. Which of the following is the correct way to declare a procedure in VHDL?

easy

A. procedure my_proc() begin
-- code
end procedure;

B. procedure my_proc is
begin
-- code
end procedure;

C. procedure my_proc is
-- code
end;

D. procedure my_proc is
begin
-- code
end;

Solution

1. Step 1: Recall VHDL procedure syntax

   A procedure declaration uses the syntax: procedure name is begin ... end procedure;.

2. Step 2: Check each option

   procedure my_proc is begin -- code end procedure; matches the correct syntax with is, begin, and end procedure;. Options B, C, and D have syntax errors or missing keywords.

3. Final Answer:

   procedure my_proc is begin -- code end procedure; -> Option B

4. Quick Check:

   Procedure syntax = procedure my_proc is begin -- code end procedure; [OK]

Hint: Procedure ends with 'end procedure;' [OK]

Common Mistakes:

• Omitting 'procedure' keyword at the end
• Using parentheses after procedure name
• Ending with just 'end;' instead of 'end procedure;'

3. What will be the output of the following VHDL procedure call?

procedure add_one(signal x : inout integer) is
begin
  x <= x + 1;
end procedure;

signal val : integer := 5;
begin
  add_one(val);
  -- What is val now?
end;

medium

A. 5

B. 7

C. 6

D. Error: procedure call syntax

Solution

1. Step 1: Understand procedure behavior

   The procedure add_one takes a signal x as inout and increments it by 1.

2. Step 2: Apply procedure to signal val

   Initially, val is 5. After calling add_one(val);, val becomes 5 + 1 = 6.

3. Final Answer:

   6 -> Option C

4. Quick Check:

   5 + 1 = 6 [OK]

Hint: Inout parameter changes value inside procedure [OK]

Common Mistakes:

• Assuming input parameters cannot change
• Confusing procedure call syntax
• Forgetting procedure modifies signal

4. Identify the error in this procedure declaration:

procedure multiply_by_two(x : in integer; y : out integer) is
begin
  y := x * 2;
end;

medium

A. Procedure must end with 'end procedure;' not just 'end;'

B. Procedure body cannot assign values to 'out' parameters

C. Parameters cannot have modes like 'in' or 'out'

D. Missing 'procedure' keyword before 'multiply_by_two'

Solution

1. Step 1: Check procedure ending syntax

   In VHDL, a procedure must end with end procedure; not just end;.

2. Step 2: Verify other parts

   The procedure keyword is present, parameter modes are allowed, and assigning to 'out' parameters is valid.

3. Final Answer:

   Procedure must end with 'end procedure;' not just 'end;' -> Option A

4. Quick Check:

   Procedure ends with 'end procedure;' [OK]

Hint: Procedure must end with 'end procedure;' [OK]

Common Mistakes:

• Ending procedure with just 'end;'
• Thinking parameter modes are not allowed
• Confusing procedure and function endings

5. You want to create a procedure that swaps two integer signals a and b. Which of the following is the correct procedure declaration and usage?

hard

A. procedure swap(signal x, y : in integer) is
variable temp : integer;
begin
temp := x;
x := y;
y := temp;
end procedure;

-- Usage: swap(a, b);

B. procedure swap(signal x, y : out integer) is
variable temp : integer;
begin
temp := x;
x := y;
y := temp;
end procedure;

-- Usage: swap(a, b);

C. procedure swap(x, y : integer) is
variable temp : integer;
begin
temp := x;
x := y;
y := temp;
end procedure;

-- Usage: swap(a, b);

D. procedure swap(signal x, y : inout integer) is
variable temp : integer;
begin
temp := x;
x <= y;
y <= temp;
end procedure;

-- Usage: swap(a, b);

Solution

1. Step 1: Determine correct parameter modes for swapping

   To swap values, both parameters must be inout or signal with mode allowing read and write. 'inout' is correct.

2. Step 2: Check procedure declaration and usage

   procedure swap(signal x, y : inout integer) is variable temp : integer; begin temp := x; x <= y; y <= temp; end procedure; -- Usage: swap(a, b); declares parameters as signal x, y : inout integer and uses a temporary variable to swap values correctly. Usage is correct.

3. Final Answer:

   procedure swap(signal x, y : inout integer) is variable temp : integer; begin temp := x; x <= y; y <= temp; end procedure; -- Usage: swap(a, b); -> Option D

4. Quick Check:

   Swap needs inout parameters [OK]

Hint: Use 'inout' mode to modify both parameters [OK]

Common Mistakes:

• Using 'in' mode which is read-only
• Using 'out' mode which cannot read input
• Omitting 'signal' keyword for signals