Procedure declaration and usage in VHDL - Deep Dive

Overview - Procedure declaration and usage

What is it?

In VHDL, a procedure is a reusable block of code that performs a specific task. It is declared once and can be called multiple times within a design to avoid repeating code. Procedures can have input and output parameters to exchange data with the calling code. They help organize complex designs by breaking them into smaller, manageable pieces.

Why it matters

Procedures exist to make VHDL code cleaner, easier to read, and maintain. Without procedures, designers would have to write the same code repeatedly, increasing errors and making changes difficult. Procedures save time and reduce mistakes by reusing tested code blocks, which is crucial in hardware design where reliability matters.

Where it fits

Before learning procedures, you should understand basic VHDL syntax, signals, variables, and processes. After mastering procedures, you can learn functions, packages, and advanced modular design techniques to build complex hardware efficiently.

Mental Model

Core Idea

A procedure is like a mini-machine inside your VHDL code that you can build once and use many times to perform a specific job.

Think of it like...

Imagine a coffee machine that you set up once and then press a button whenever you want coffee. The procedure is the coffee machine, and calling it is pressing the button to get coffee without rebuilding the machine each time.

┌───────────────────────────┐
│        Procedure          │
│  ┌─────────────────────┐  │
│  │  Code block to do    │  │
│  │  a specific task     │  │
│  └─────────────────────┘  │
└─────────────┬─────────────┘
              │
      ┌───────▼────────┐
      │ Call procedure  │
      │ from main code  │
      └─────────────────┘

Build-Up - 7 Steps

1

Foundation

Understanding basic procedure syntax

Concept: Learn how to declare a simple procedure with no parameters in VHDL.

A procedure declaration starts with the keyword 'procedure' followed by its name and ends with 'end procedure;'. It is placed inside a package or architecture body. For example: procedure say_hello is begin report "Hello from procedure!"; end procedure say_hello;

Result

You have a named block of code that prints a message when called.

Knowing the basic syntax is the first step to using procedures effectively in VHDL.

2

Foundation

Calling a procedure inside a process

Concept: Learn how to invoke a declared procedure within a process block.

Inside a process, you can call a procedure by its name followed by parentheses. For example: process begin say_hello; wait; end process;

Result

When the process runs, it executes the procedure code and prints the message.

Understanding how to call procedures lets you reuse code blocks inside your design.

3

Intermediate

Using input parameters in procedures

🤔Before reading on: do you think procedures can change the input values passed to them? Commit to your answer.

Concept: Procedures can accept input parameters to receive data from the caller, but these inputs cannot be changed inside the procedure.

You declare input parameters with the keyword 'in' and specify their type. For example: procedure print_value(val : in integer) is begin report "Value is " & integer'image(val); end procedure print_value; Call it with: print_value(42);

Result

The procedure prints 'Value is 42' when called.

Knowing input parameters lets you write flexible procedures that work with different data.

4

Intermediate

Output and inout parameters explained

🤔Before reading on: can a procedure modify a variable passed as an output parameter? Commit to your answer.

Concept: Procedures can have output ('out') and bidirectional ('inout') parameters to send data back to the caller or modify it.

An 'out' parameter lets the procedure assign a value that the caller receives. An 'inout' parameter can be read and changed inside the procedure. Example: procedure increment(val : inout integer) is begin val := val + 1; end procedure increment; Usage: variable x : integer := 5; increment(x); -- x becomes 6

Result

The variable passed is updated by the procedure.

Understanding output parameters is key to procedures that communicate results back to the caller.

5

Intermediate

Parameter modes and their effects

Concept: Learn how 'in', 'out', and 'inout' parameter modes control data flow between caller and procedure.

'in' parameters are read-only inside the procedure. 'out' parameters are write-only and must be assigned before procedure ends. 'inout' parameters can be read and written. Example: procedure swap(a : inout integer; b : inout integer) is variable temp : integer; begin temp := a; a := b; b := temp; end procedure swap;

Result

The swap procedure exchanges the values of two variables.

Knowing parameter modes prevents bugs and clarifies how data moves in your design.

6

Advanced

Procedures inside packages for reuse

🤔Before reading on: do you think procedures declared inside packages can be used across multiple designs? Commit to your answer.

Concept: Declaring procedures inside packages allows sharing and reusing them in many designs by importing the package.

Create a package: package utils is procedure print_value(val : in integer); end package utils; package body utils is procedure print_value(val : in integer) is begin report "Value: " & integer'image(val); end procedure print_value; end package body utils; Use in design: library work; use work.utils.all; process begin print_value(10); wait; end process;

Result

The procedure is reusable across designs that include the package.

Using packages organizes code and promotes modular, maintainable designs.

7

Expert

Procedure call overhead and synthesis impact

🤔Before reading on: do you think procedure calls always create separate hardware blocks? Commit to your answer.

Concept: Procedures are a code organization tool and do not necessarily create separate hardware; synthesis tools inline procedure code where possible.

When synthesizing, the procedure code is inserted where called, not as a separate block. This means no extra hardware cost for calling procedures multiple times. However, recursive procedures are not supported in synthesis. Example: procedure add_one(signal x : inout integer) is begin x := x + 1; end procedure add_one; Synthesis tool replaces calls with the addition operation directly.

Result

Procedures help code clarity without hardware overhead.

Understanding synthesis behavior prevents misconceptions about hardware cost and helps write efficient VHDL.

Under the Hood

Procedures in VHDL are stored as named blocks of code in the design's intermediate representation. When the design is simulated or synthesized, calls to procedures are replaced by the procedure's code inline, similar to copying and pasting the code at each call site. This means no runtime overhead or separate hardware unless the procedure contains sequential logic. Parameters are passed by value or reference depending on their mode, controlling how data flows between caller and procedure.

Why designed this way?

VHDL was designed to describe hardware behavior clearly and modularly. Procedures allow designers to write reusable code blocks without changing hardware structure. Inline expansion of procedures avoids extra hardware cost and keeps designs efficient. This design balances code clarity with hardware synthesis constraints, unlike software functions that run on CPUs.

┌───────────────┐       ┌───────────────┐
│   Caller      │       │  Procedure    │
│  Code block   │──────▶│  Code block   │
└───────────────┘       └───────────────┘
         │                      ▲
         │ Inline expansion     │
         └──────────────────────┘

Myth Busters - 4 Common Misconceptions

Quick: Does calling a procedure in VHDL always create a separate hardware block? Commit to yes or no.

Common Belief: Calling a procedure creates a separate hardware block each time it is used.

Reality: Procedure calls are inlined by synthesis tools, so no extra hardware block is created just by calling a procedure.

Why it matters: Believing this leads to unnecessary fear of using procedures and writing duplicated code instead, reducing maintainability.

Quick: Can procedures in VHDL return values like functions? Commit to yes or no.

Common Belief: Procedures can return values directly like functions.

Reality: Procedures do not return values; they use output or inout parameters to send data back.

Why it matters: Confusing procedures with functions causes syntax errors and design confusion.

Quick: Can you use recursive procedures in synthesizable VHDL? Commit to yes or no.

Common Belief: Recursive procedures are allowed and synthesizable in VHDL.

Reality: Recursive procedures are not supported for synthesis and will cause errors or unsupported designs.

Why it matters: Trying to use recursion in hardware design leads to synthesis failures and wasted effort.

Quick: Are 'out' parameters readable inside the procedure? Commit to yes or no.

Common Belief: 'out' parameters can be read and written inside the procedure.

Reality: 'out' parameters are write-only inside the procedure and should not be read before assignment.

Why it matters: Misusing 'out' parameters causes simulation mismatches and unexpected behavior.

Expert Zone

1

Procedures with 'inout' parameters can cause subtle bugs if the caller and procedure share the same signal or variable, leading to unexpected data overwrites.

2

Synthesis tools may optimize away procedure calls by inlining, but simulation tools keep procedure boundaries, which can cause differences in debugging behavior.

3

Procedures inside packages can be overloaded by declaring multiple procedures with the same name but different parameter lists, enabling polymorphic behavior.

When NOT to use

Avoid using procedures when you need a single return value; use functions instead. Also, do not use recursive procedures in synthesizable code. For simple combinational expressions, functions are more appropriate. Use procedures mainly for multi-step operations or when multiple outputs are needed.

Production Patterns

In real-world designs, procedures are used to encapsulate common tasks like signal initialization, data formatting, or error checking. They are often grouped in utility packages shared across projects. Designers use procedures to reduce code duplication and improve readability, especially in testbenches and complex state machines.

Connections

Functions in VHDL

Procedures and functions both modularize code but differ in return behavior and usage.

Understanding procedures clarifies when to use functions for single output versus procedures for multiple outputs or side effects.

Modular programming in software engineering

Procedures in VHDL are similar to subroutines or methods in software that promote code reuse and clarity.

Recognizing this connection helps software developers adapt their modular thinking to hardware design.

Manufacturing assembly lines

Procedures resemble stations in an assembly line where specific tasks are done repeatedly to build a product.

This analogy helps understand how procedures break complex hardware behavior into repeatable, manageable steps.

Common Pitfalls

#1 Trying to read an 'out' parameter inside a procedure before assigning it.

Wrong approach:

procedure example(out_val : out integer) is
begin
if out_val = 0 then -- wrong: reading 'out' parameter
out_val := 1;
end if;
end procedure example;

Correct approach:

procedure example(out_val : out integer) is
begin
out_val := 1; -- assign before reading
end procedure example;

Root cause:

Misunderstanding that 'out' parameters are write-only inside procedures.

#2 Using recursive procedure calls in synthesizable code.

Wrong approach:

procedure recurse(n : in integer) is
begin
if n > 0 then
recurse(n - 1); -- recursive call
end if;
end procedure recurse;

Correct approach:

Use iterative loops or state machines instead of recursion for synthesis.

Root cause:

Assuming software recursion works the same way in hardware design.

#3 Declaring a procedure inside a process instead of architecture or package.

Wrong approach:

process
procedure local_proc is
begin
report "Hi";
end procedure;
begin
local_proc();
wait;
end process;

Correct approach:

Declare procedures inside architecture or package bodies, not inside processes.

Root cause:

Confusing VHDL scope rules and where declarations are allowed.

Key Takeaways

Procedures in VHDL are reusable code blocks that help organize and simplify hardware descriptions.

They can have input, output, and inout parameters to exchange data with the calling code.

Procedure calls are inlined during synthesis, so they do not add hardware overhead by themselves.

Understanding parameter modes and proper declaration scope is essential to avoid common errors.

Procedures complement functions and packages to build modular, maintainable VHDL designs.

Practice

1. What is the main purpose of a procedure in VHDL?

easy

A. To group a set of instructions for reuse

B. To declare a new signal

C. To define a new entity

D. To assign values to constants

Solution

1. Step 1: Understand what a procedure does

   A procedure groups instructions to perform a specific task that can be reused multiple times in the code.

2. Step 2: Compare with other options

   Declaring signals, entities, or assigning constants are different VHDL tasks, not the main purpose of procedures.

3. Final Answer:

   To group a set of instructions for reuse -> Option A

4. Quick Check:

   Procedure = reusable instruction group [OK]

Hint: Procedures bundle instructions for reuse [OK]

Common Mistakes:

• Confusing procedures with signal declarations
• Thinking procedures define entities
• Assuming procedures assign constants

2. Which of the following is the correct way to declare a procedure in VHDL?

easy

A. procedure my_proc() begin
-- code
end procedure;

B. procedure my_proc is
begin
-- code
end procedure;

C. procedure my_proc is
-- code
end;

D. procedure my_proc is
begin
-- code
end;

Solution

1. Step 1: Recall VHDL procedure syntax

   A procedure declaration uses the syntax: procedure name is begin ... end procedure;.

2. Step 2: Check each option

   procedure my_proc is begin -- code end procedure; matches the correct syntax with is, begin, and end procedure;. Options B, C, and D have syntax errors or missing keywords.

3. Final Answer:

   procedure my_proc is begin -- code end procedure; -> Option B

4. Quick Check:

   Procedure syntax = procedure my_proc is begin -- code end procedure; [OK]

Hint: Procedure ends with 'end procedure;' [OK]

Common Mistakes:

• Omitting 'procedure' keyword at the end
• Using parentheses after procedure name
• Ending with just 'end;' instead of 'end procedure;'

3. What will be the output of the following VHDL procedure call?

procedure add_one(signal x : inout integer) is
begin
  x <= x + 1;
end procedure;

signal val : integer := 5;
begin
  add_one(val);
  -- What is val now?
end;

medium

A. 5

B. 7

C. 6

D. Error: procedure call syntax

Solution

1. Step 1: Understand procedure behavior

   The procedure add_one takes a signal x as inout and increments it by 1.

2. Step 2: Apply procedure to signal val

   Initially, val is 5. After calling add_one(val);, val becomes 5 + 1 = 6.

3. Final Answer:

   6 -> Option C

4. Quick Check:

   5 + 1 = 6 [OK]

Hint: Inout parameter changes value inside procedure [OK]

Common Mistakes:

• Assuming input parameters cannot change
• Confusing procedure call syntax
• Forgetting procedure modifies signal

4. Identify the error in this procedure declaration:

procedure multiply_by_two(x : in integer; y : out integer) is
begin
  y := x * 2;
end;

medium

A. Procedure must end with 'end procedure;' not just 'end;'

B. Procedure body cannot assign values to 'out' parameters

C. Parameters cannot have modes like 'in' or 'out'

D. Missing 'procedure' keyword before 'multiply_by_two'

Solution

1. Step 1: Check procedure ending syntax

   In VHDL, a procedure must end with end procedure; not just end;.

2. Step 2: Verify other parts

   The procedure keyword is present, parameter modes are allowed, and assigning to 'out' parameters is valid.

3. Final Answer:

   Procedure must end with 'end procedure;' not just 'end;' -> Option A

4. Quick Check:

   Procedure ends with 'end procedure;' [OK]

Hint: Procedure must end with 'end procedure;' [OK]

Common Mistakes:

• Ending procedure with just 'end;'
• Thinking parameter modes are not allowed
• Confusing procedure and function endings

5. You want to create a procedure that swaps two integer signals a and b. Which of the following is the correct procedure declaration and usage?

hard

A. procedure swap(signal x, y : in integer) is
variable temp : integer;
begin
temp := x;
x := y;
y := temp;
end procedure;

-- Usage: swap(a, b);

B. procedure swap(signal x, y : out integer) is
variable temp : integer;
begin
temp := x;
x := y;
y := temp;
end procedure;

-- Usage: swap(a, b);

C. procedure swap(x, y : integer) is
variable temp : integer;
begin
temp := x;
x := y;
y := temp;
end procedure;

-- Usage: swap(a, b);

D. procedure swap(signal x, y : inout integer) is
variable temp : integer;
begin
temp := x;
x <= y;
y <= temp;
end procedure;

-- Usage: swap(a, b);

Solution

1. Step 1: Determine correct parameter modes for swapping

   To swap values, both parameters must be inout or signal with mode allowing read and write. 'inout' is correct.

2. Step 2: Check procedure declaration and usage

   procedure swap(signal x, y : inout integer) is variable temp : integer; begin temp := x; x <= y; y <= temp; end procedure; -- Usage: swap(a, b); declares parameters as signal x, y : inout integer and uses a temporary variable to swap values correctly. Usage is correct.

3. Final Answer:

   procedure swap(signal x, y : inout integer) is variable temp : integer; begin temp := x; x <= y; y <= temp; end procedure; -- Usage: swap(a, b); -> Option D

4. Quick Check:

   Swap needs inout parameters [OK]

Hint: Use 'inout' mode to modify both parameters [OK]

Common Mistakes:

• Using 'in' mode which is read-only
• Using 'out' mode which cannot read input
• Omitting 'signal' keyword for signals