Timer with terminal count output in VHDL - Step-by-Step Execution

Concept Flow - Timer with terminal count output

Start Timer

↓

Load Counter with Max Value

↓

Count Down Each Clock Cycle

↓

Check if Counter = 0?

No→Continue Counting

Yes↓

Set Terminal Count Output High

↓

Stop or Reload Counter

The timer starts by loading a max count value, then counts down each clock cycle until it reaches zero, triggering the terminal count output.

Execution Sample

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity timer is
  port(clk: in std_logic; reset: in std_logic; tc: out std_logic);
end timer;

architecture rtl of timer is
  signal count: integer := 5;
begin
  process(clk, reset) is
  begin
    if reset = '1' then
      count <= 5;
      tc <= '0';
    elsif rising_edge(clk) then
      if count > 0 then
        count <= count - 1;
        tc <= '0';
      else
        tc <= '1';
      end if;
    end if;
  end process;
end rtl;

This VHDL code defines a timer that counts down from 5 to 0 on each clock cycle and sets terminal count output high when it reaches zero.

Execution Table

Step	clk rising_edge	reset	count before	count after	tc output	Action
1	Yes	1	5	5	0	Reset active: count set to 5, tc=0
2	Yes	0	5	4	0	Count > 0: decrement count to 4, tc=0
3	Yes	0	4	3	0	Count > 0: decrement count to 3, tc=0
4	Yes	0	3	2	0	Count > 0: decrement count to 2, tc=0
5	Yes	0	2	1	0	Count > 0: decrement count to 1, tc=0
6	Yes	0	1	0	0	Count > 0: decrement count to 0, tc=0
7	Yes	0	0	0	1	Count = 0: tc set to 1
8	Yes	0	0	0	1	Count = 0: tc remains 1
9	No	0	0	0	1	No clock edge: no change
10	Yes	1	0	5	0	Reset active again: count=5, tc=0

💡 Simulation stops after reset reinitializes the counter.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	After 8	After 9	After 10
count	5	5	4	3	2	1	0	0	0	0	5
tc	0	0	0	0	0	0	0	1	1	1	0

Key Moments - 2 Insights

Why does the terminal count output (tc) stay '0' when count reaches 0 at step 6?

At step 6, count is decremented from 1 to 0, but tc is set to '1' only in the next clock cycle when count is already 0, as shown in step 7 of the execution_table.

What happens if reset is active during a clock rising edge?

When reset is '1' during a clock rising edge (steps 1 and 10), the counter is immediately set back to 5 and tc is cleared to '0', overriding normal counting behavior.

Visual Quiz - 3 Questions

Look at the execution_table at step 4. What is the value of count after the clock rising edge?

A 2

B 4

C 3

D 5

💡 Hint

Check the 'count after' column at step 4 in the execution_table.

At which step does the terminal count output (tc) first become '1'?

A Step 6

B Step 5

C Step 7

D Step 8

💡 Hint

Look at the 'tc output' column in the execution_table to find when it changes to '1'.

If the reset signal is never activated, what would happen to the count variable after step 7?

A It resets to 5 automatically.

B It stays at 0 and tc stays '1'.

C It counts up from 0.

D It becomes undefined.

💡 Hint

Refer to the execution_table rows 7 and 8 where count is 0 and tc is 1 without reset.

Concept Snapshot

Timer with terminal count output in VHDL:
- Initialize counter to max value
- On each clock rising edge, decrement if > 0
- When counter reaches 0, set terminal count (tc) output high
- Reset sets counter back to max and clears tc
- Terminal count signals timer completion

Full Transcript

This VHDL timer counts down from a preset value on each clock rising edge. When reset is active, the counter resets to the initial value and terminal count output is cleared. Each clock cycle, if the counter is greater than zero, it decrements by one and terminal count remains low. When the counter reaches zero, terminal count output is set high, indicating the timer has finished counting. The execution table shows step-by-step how count and terminal count output change with clock and reset signals. Key moments clarify why terminal count output changes only after count reaches zero and how reset affects the timer. The visual quiz tests understanding of count values and terminal count output timing.

Practice

1. What does the terminal count output signal in a VHDL timer?

easy

A. The timer has reached its preset count value

B. The timer is reset to zero

C. The clock signal is inactive

D. The timer is paused

Solution

1. Step 1: Understand the timer function

   A timer counts clock pulses until it reaches a preset value.

2. Step 2: Define terminal count output meaning

   The terminal count output signals when the timer hits that preset value.

3. Final Answer:

   The timer has reached its preset count value -> Option A

4. Quick Check:

   Terminal count = timer reached preset [OK]

Hint: Terminal count means timer reached set value [OK]

Common Mistakes:

• Confusing terminal count with reset signal
• Thinking terminal count means timer stopped
• Mixing terminal count with clock inactivity

2. Which of the following is the correct VHDL syntax to declare a terminal count output signal named tc as a std_logic?

easy

A. signal tc std_logic;

B. signal tc : std_logic

C. signal tc : std_logic;

D. signal tc = std_logic;

Solution

1. Step 1: Recall VHDL signal declaration syntax

   Signals are declared with keyword 'signal', name, colon, type, and semicolon.

2. Step 2: Check each option

   signal tc : std_logic; uses correct syntax: 'signal tc : std_logic;'. Others miss colon or semicolon or use wrong assignment.

3. Final Answer:

   signal tc : std_logic; -> Option C

4. Quick Check:

   Signal declaration = signal name : type; [OK]

Hint: Signal declaration needs colon and semicolon [OK]

Common Mistakes:

• Omitting colon between name and type
• Forgetting semicolon at end
• Using equals sign instead of colon

3. Given this VHDL process for a timer:

process(clk, reset)
begin
  if reset = '1' then
    count <= 0;
    tc <= '0';
  elsif rising_edge(clk) then
    if count = 9 then
      count <= 0;
      tc <= '1';
    else
      count <= count + 1;
      tc <= '0';
    end if;
  end if;
end process;

What is the value of tc after 10 clock cycles without reset?

medium

A. '1' on the 10th cycle, '0' otherwise

B. '0' on all cycles

C. '1' on every cycle

D. '1' on the 9th cycle only

Solution

1. Step 1: Analyze counting and terminal count logic

   The counter counts from 0 to 9. When count = 9, tc is set to '1' and count resets to 0.

2. Step 2: Trace tc output over 10 clock cycles

   For cycles 1 to 9, tc = '0'. On the 10th cycle (count=9), tc = '1'. Then count resets.

3. Final Answer:

   '1' on the 10th cycle, '0' otherwise -> Option A

4. Quick Check:

   tc = '1' at terminal count (10th cycle) [OK]

Hint: tc is '1' only when count reaches max [OK]

Common Mistakes:

• Assuming tc is '1' every cycle
• Confusing count value for tc output
• Forgetting count resets after terminal count

4. Identify the error in this VHDL timer process:

process(clk, reset)
begin
  if reset = '1' then
    count <= 0;
    tc <= '0';
  elsif clk'event and clk = '1' then
    if count = 10 then
      count <= 0;
      tc <= '1';
    else
      count <= count + 1;
      tc <= '0';
    end if;
  end if;
end process;

medium

A. tc signal should be declared as integer

B. Using clk'event and clk = '1' instead of rising_edge(clk)

C. Reset condition should be checked after clock event

D. Count comparison should be count = 9, not 10

Solution

1. Step 1: Check count comparison logic

   The timer counts from 0, so max count for 10 cycles is 9, not 10.

2. Step 2: Understand effect of wrong count value

   If count = 10 is checked, terminal count never triggers because count resets at 9+1=10, causing off-by-one error.

3. Final Answer:

   Count comparison should be count = 9, not 10 -> Option D

4. Quick Check:

   Max count for 10 cycles = 9 [OK]

Hint: Count max is one less than total cycles [OK]

Common Mistakes:

• Using clk'event instead of rising_edge(clk) (still valid but less modern)
• Checking reset after clock event
• Declaring tc as wrong type

5. You want to design a VHDL timer that counts from 0 to 15 and sets terminal count output tc high for exactly one clock cycle when count reaches 15. Which code snippet correctly implements this behavior?

hard

A. if count = 15 then
count <= 15;
tc <= '1';
else
count <= count + 1;
tc <= '0';
end if;

B. if count = 15 then
count <= 0;
tc <= '1';
else
count <= count + 1;
tc <= '0';
end if;

C. if count >= 15 then
tc <= '1';
else
count <= count + 1;
tc <= '0';
end if;

D. if count = 14 then
count <= 0;
tc <= '1';
else
count <= count + 1;
tc <= '0';
end if;

Solution

1. Step 1: Understand terminal count condition

   The timer must reset count to 0 and set tc='1' exactly when count = 15.

2. Step 2: Evaluate each option

   if count = 15 then count <= 0; tc <= '1'; else count <= count + 1; tc <= '0'; end if; resets count at 15 and sets tc='1' for one cycle. if count = 15 then count <= 15; tc <= '1'; else count <= count + 1; tc <= '0'; end if; holds count at 15, causing no reset. if count >= 15 then tc <= '1'; else count <= count + 1; tc <= '0'; end if; does not reset count, causing tc to remain high for multiple cycles. if count = 14 then count <= 0; tc <= '1'; else count <= count + 1; tc <= '0'; end if; triggers at 14, which is incorrect.

3. Final Answer:

   if count = 15 then count <= 0; tc <= '1'; else count <= count + 1; tc <= '0'; end if; -> Option B

4. Quick Check:

   tc high only at count = 15, then reset [OK]

Hint: Reset count and set tc only at exact max count [OK]

Common Mistakes:

• Not resetting count after terminal count
• Setting tc high for multiple cycles
• Triggering terminal count too early