Timer with terminal count output in VHDL - Mini Project: Build & Apply

Timer with terminal count output

📖 Scenario: You are designing a simple timer circuit in VHDL that counts clock pulses up to a set limit and then signals when the count reaches that limit.

🎯 Goal: Build a VHDL timer that counts from 0 up to a terminal count value and outputs a signal when the terminal count is reached.

📋 What You'll Learn

Create a signal to hold the current count.

Create a constant for the terminal count value.

Implement a process that increments the count on each clock rising edge.

Output a terminal count signal when the count reaches the terminal count.

💡 Why This Matters

🌍 Real World

Timers are used in digital circuits to measure time intervals, generate delays, or create timed events.

💼 Career

Understanding timers and counters is essential for hardware design engineers working with FPGAs or ASICs.

1

Create the count signal

Create a signal called count of type integer initialized to 0 inside the architecture.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Timer is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           terminal_count : out STD_LOGIC);
end Timer;

architecture Behavioral of Timer is
    -- Declare count signal here
    -- Your code here
begin

end Behavioral;

Hint

Use signal count : integer := 0; inside the architecture declaration.

2

Create the terminal count constant

Create a constant called TERMINAL_COUNT of type integer with value 10 inside the architecture.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Timer is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           terminal_count : out STD_LOGIC);
end Timer;

architecture Behavioral of Timer is
    signal count : integer := 0;
    -- Declare TERMINAL_COUNT constant here
    -- Your code here
begin

end Behavioral;

Hint

Use constant TERMINAL_COUNT : integer := 10; inside the architecture declaration.

3

Implement the counting process

Write a process sensitive to clk and reset that increments count by 1 on each rising edge of clk. Reset count to 0 when reset is '1'. When count reaches TERMINAL_COUNT, reset count to 0.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Timer is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           terminal_count : out STD_LOGIC);
end Timer;

architecture Behavioral of Timer is
    signal count : integer := 0;
    constant TERMINAL_COUNT : integer := 10;
begin
    -- Add counting process here
    -- Your code here
end Behavioral;

Hint

Use a process with if reset = '1' to reset count, and elsif rising_edge(clk) to increment count or reset when terminal count is reached.

4

Output the terminal count signal

Assign terminal_count output to '1' when count equals TERMINAL_COUNT, otherwise '0'. Use a concurrent signal assignment.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Timer is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           terminal_count : out STD_LOGIC);
end Timer;

architecture Behavioral of Timer is
    signal count : integer := 0;
    constant TERMINAL_COUNT : integer := 10;
begin
    process(clk, reset)
    begin
        if reset = '1' then
            count <= 0;
        elsif rising_edge(clk) then
            if count = TERMINAL_COUNT then
                count <= 0;
            else
                count <= count + 1;
            end if;
        end if;
    end process;
    -- Assign terminal_count output here
    -- Your code here
end Behavioral;

Hint

Use a concurrent assignment: terminal_count <= '1' when count = TERMINAL_COUNT else '0';

Practice

1. What does the terminal count output signal in a VHDL timer?

easy

A. The timer has reached its preset count value

B. The timer is reset to zero

C. The clock signal is inactive

D. The timer is paused

Solution

1. Step 1: Understand the timer function

   A timer counts clock pulses until it reaches a preset value.

2. Step 2: Define terminal count output meaning

   The terminal count output signals when the timer hits that preset value.

3. Final Answer:

   The timer has reached its preset count value -> Option A

4. Quick Check:

   Terminal count = timer reached preset [OK]

Hint: Terminal count means timer reached set value [OK]

Common Mistakes:

• Confusing terminal count with reset signal
• Thinking terminal count means timer stopped
• Mixing terminal count with clock inactivity

2. Which of the following is the correct VHDL syntax to declare a terminal count output signal named tc as a std_logic?

easy

A. signal tc std_logic;

B. signal tc : std_logic

C. signal tc : std_logic;

D. signal tc = std_logic;

Solution

1. Step 1: Recall VHDL signal declaration syntax

   Signals are declared with keyword 'signal', name, colon, type, and semicolon.

2. Step 2: Check each option

   signal tc : std_logic; uses correct syntax: 'signal tc : std_logic;'. Others miss colon or semicolon or use wrong assignment.

3. Final Answer:

   signal tc : std_logic; -> Option C

4. Quick Check:

   Signal declaration = signal name : type; [OK]

Hint: Signal declaration needs colon and semicolon [OK]

Common Mistakes:

• Omitting colon between name and type
• Forgetting semicolon at end
• Using equals sign instead of colon

3. Given this VHDL process for a timer:

process(clk, reset)
begin
  if reset = '1' then
    count <= 0;
    tc <= '0';
  elsif rising_edge(clk) then
    if count = 9 then
      count <= 0;
      tc <= '1';
    else
      count <= count + 1;
      tc <= '0';
    end if;
  end if;
end process;

What is the value of tc after 10 clock cycles without reset?

medium

A. '1' on the 10th cycle, '0' otherwise

B. '0' on all cycles

C. '1' on every cycle

D. '1' on the 9th cycle only

Solution

1. Step 1: Analyze counting and terminal count logic

   The counter counts from 0 to 9. When count = 9, tc is set to '1' and count resets to 0.

2. Step 2: Trace tc output over 10 clock cycles

   For cycles 1 to 9, tc = '0'. On the 10th cycle (count=9), tc = '1'. Then count resets.

3. Final Answer:

   '1' on the 10th cycle, '0' otherwise -> Option A

4. Quick Check:

   tc = '1' at terminal count (10th cycle) [OK]

Hint: tc is '1' only when count reaches max [OK]

Common Mistakes:

• Assuming tc is '1' every cycle
• Confusing count value for tc output
• Forgetting count resets after terminal count

4. Identify the error in this VHDL timer process:

process(clk, reset)
begin
  if reset = '1' then
    count <= 0;
    tc <= '0';
  elsif clk'event and clk = '1' then
    if count = 10 then
      count <= 0;
      tc <= '1';
    else
      count <= count + 1;
      tc <= '0';
    end if;
  end if;
end process;

medium

A. tc signal should be declared as integer

B. Using clk'event and clk = '1' instead of rising_edge(clk)

C. Reset condition should be checked after clock event

D. Count comparison should be count = 9, not 10

Solution

1. Step 1: Check count comparison logic

   The timer counts from 0, so max count for 10 cycles is 9, not 10.

2. Step 2: Understand effect of wrong count value

   If count = 10 is checked, terminal count never triggers because count resets at 9+1=10, causing off-by-one error.

3. Final Answer:

   Count comparison should be count = 9, not 10 -> Option D

4. Quick Check:

   Max count for 10 cycles = 9 [OK]

Hint: Count max is one less than total cycles [OK]

Common Mistakes:

• Using clk'event instead of rising_edge(clk) (still valid but less modern)
• Checking reset after clock event
• Declaring tc as wrong type

5. You want to design a VHDL timer that counts from 0 to 15 and sets terminal count output tc high for exactly one clock cycle when count reaches 15. Which code snippet correctly implements this behavior?

hard

A. if count = 15 then
count <= 15;
tc <= '1';
else
count <= count + 1;
tc <= '0';
end if;

B. if count = 15 then
count <= 0;
tc <= '1';
else
count <= count + 1;
tc <= '0';
end if;

C. if count >= 15 then
tc <= '1';
else
count <= count + 1;
tc <= '0';
end if;

D. if count = 14 then
count <= 0;
tc <= '1';
else
count <= count + 1;
tc <= '0';
end if;

Solution

1. Step 1: Understand terminal count condition

   The timer must reset count to 0 and set tc='1' exactly when count = 15.

2. Step 2: Evaluate each option

   if count = 15 then count <= 0; tc <= '1'; else count <= count + 1; tc <= '0'; end if; resets count at 15 and sets tc='1' for one cycle. if count = 15 then count <= 15; tc <= '1'; else count <= count + 1; tc <= '0'; end if; holds count at 15, causing no reset. if count >= 15 then tc <= '1'; else count <= count + 1; tc <= '0'; end if; does not reset count, causing tc to remain high for multiple cycles. if count = 14 then count <= 0; tc <= '1'; else count <= count + 1; tc <= '0'; end if; triggers at 14, which is incorrect.

3. Final Answer:

   if count = 15 then count <= 0; tc <= '1'; else count <= count + 1; tc <= '0'; end if; -> Option B

4. Quick Check:

   tc high only at count = 15, then reset [OK]

Hint: Reset count and set tc only at exact max count [OK]

Common Mistakes:

• Not resetting count after terminal count
• Setting tc high for multiple cycles
• Triggering terminal count too early