Timer with terminal count output in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the clock input signal.

VHDL

entity timer is
  Port (
    [1] : in std_logic;
    reset : in std_logic;
    terminal_count : out std_logic
  );
end timer;

Drag options to blanks, or click blank then click option'

Aclk_in

Bclk

Cclock

Dclock_in

Attempts:

3 left

💡 Hint

Common Mistakes

Using output direction for clock signal

Using a signal name that is not descriptive

The clock input signal is commonly named clock in VHDL entities.

2fill in blank

medium

Complete the code to define the counter signal as a 4-bit unsigned type.

VHDL

architecture Behavioral of timer is
  signal counter : [1](3 downto 0) := (others => '0');
begin
  -- process here
end Behavioral;

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Astd_logic_vector

Bbit_vector

Cinteger

Dunsigned

Attempts:

3 left

💡 Hint

Common Mistakes

Using std_logic_vector without numeric operations

Using integer type for signal declaration

The unsigned type from the numeric_std package is used for arithmetic on bit vectors representing numbers.

3fill in blank

hard

Fix the error in the process sensitivity list to include the clock signal.

VHDL

process([1], reset)
begin
  if reset = '1' then
    counter <= (others => '0');
  elsif rising_edge(clock) then
    -- counter logic
  end if;
end process;

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Aclk

Bclock

Cclk_signal

Dclk_in

Attempts:

3 left

💡 Hint

Common Mistakes

Using a wrong clock signal name in sensitivity list

Omitting the clock signal from sensitivity list

The sensitivity list must include the clock signal named clock to detect rising edges properly.

4fill in blank

hard

Fill both blanks to complete the terminal count logic and counter increment.

VHDL

process(clock, reset)
begin
  if reset = '1' then
    counter <= (others => '0');
    terminal_count <= '0';
  elsif rising_edge(clock) then
    if counter = [1] then
      terminal_count <= '1';
      counter <= (others => '0');
    else
      counter <= counter [2] 1;
      terminal_count <= '0';
    end if;
  end if;
end process;

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A15

B+

C-

D16

Attempts:

3 left

💡 Hint

Common Mistakes

Using 16 as terminal count (out of range)

Using minus operator instead of plus for increment

The terminal count is 15 for a 4-bit counter. The counter increments by 1 using the + operator.

5fill in blank

hard

Fill all three blanks to complete the output assignment and counter reset logic.

VHDL

process(clock, reset)
begin
  if reset = '1' then
    counter <= (others => '0');
    terminal_count <= '0';
  elsif rising_edge(clock) then
    if counter = [1] then
      terminal_count <= [2];
      counter <= [3];
    else
      counter <= counter + 1;
      terminal_count <= '0';
    end if;
  end if;
end process;

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A15

B'1'

C(others => '0')

D'0'

Attempts:

3 left

💡 Hint

Common Mistakes

Using wrong terminal count value

Setting terminal_count to '0' instead of '1'

Resetting counter incorrectly

The terminal count is 15, terminal_count output is set to '1', and the counter resets to all zeros.

Practice

1. What does the terminal count output signal in a VHDL timer?

easy

A. The timer has reached its preset count value

B. The timer is reset to zero

C. The clock signal is inactive

D. The timer is paused

Solution

1. Step 1: Understand the timer function

   A timer counts clock pulses until it reaches a preset value.

2. Step 2: Define terminal count output meaning

   The terminal count output signals when the timer hits that preset value.

3. Final Answer:

   The timer has reached its preset count value -> Option A

4. Quick Check:

   Terminal count = timer reached preset [OK]

Hint: Terminal count means timer reached set value [OK]

Common Mistakes:

• Confusing terminal count with reset signal
• Thinking terminal count means timer stopped
• Mixing terminal count with clock inactivity

2. Which of the following is the correct VHDL syntax to declare a terminal count output signal named tc as a std_logic?

easy

A. signal tc std_logic;

B. signal tc : std_logic

C. signal tc : std_logic;

D. signal tc = std_logic;

Solution

1. Step 1: Recall VHDL signal declaration syntax

   Signals are declared with keyword 'signal', name, colon, type, and semicolon.

2. Step 2: Check each option

   signal tc : std_logic; uses correct syntax: 'signal tc : std_logic;'. Others miss colon or semicolon or use wrong assignment.

3. Final Answer:

   signal tc : std_logic; -> Option C

4. Quick Check:

   Signal declaration = signal name : type; [OK]

Hint: Signal declaration needs colon and semicolon [OK]

Common Mistakes:

• Omitting colon between name and type
• Forgetting semicolon at end
• Using equals sign instead of colon

3. Given this VHDL process for a timer:

process(clk, reset)
begin
  if reset = '1' then
    count <= 0;
    tc <= '0';
  elsif rising_edge(clk) then
    if count = 9 then
      count <= 0;
      tc <= '1';
    else
      count <= count + 1;
      tc <= '0';
    end if;
  end if;
end process;

What is the value of tc after 10 clock cycles without reset?

medium

A. '1' on the 10th cycle, '0' otherwise

B. '0' on all cycles

C. '1' on every cycle

D. '1' on the 9th cycle only

Solution

1. Step 1: Analyze counting and terminal count logic

   The counter counts from 0 to 9. When count = 9, tc is set to '1' and count resets to 0.

2. Step 2: Trace tc output over 10 clock cycles

   For cycles 1 to 9, tc = '0'. On the 10th cycle (count=9), tc = '1'. Then count resets.

3. Final Answer:

   '1' on the 10th cycle, '0' otherwise -> Option A

4. Quick Check:

   tc = '1' at terminal count (10th cycle) [OK]

Hint: tc is '1' only when count reaches max [OK]

Common Mistakes:

• Assuming tc is '1' every cycle
• Confusing count value for tc output
• Forgetting count resets after terminal count

4. Identify the error in this VHDL timer process:

process(clk, reset)
begin
  if reset = '1' then
    count <= 0;
    tc <= '0';
  elsif clk'event and clk = '1' then
    if count = 10 then
      count <= 0;
      tc <= '1';
    else
      count <= count + 1;
      tc <= '0';
    end if;
  end if;
end process;

medium

A. tc signal should be declared as integer

B. Using clk'event and clk = '1' instead of rising_edge(clk)

C. Reset condition should be checked after clock event

D. Count comparison should be count = 9, not 10

Solution

1. Step 1: Check count comparison logic

   The timer counts from 0, so max count for 10 cycles is 9, not 10.

2. Step 2: Understand effect of wrong count value

   If count = 10 is checked, terminal count never triggers because count resets at 9+1=10, causing off-by-one error.

3. Final Answer:

   Count comparison should be count = 9, not 10 -> Option D

4. Quick Check:

   Max count for 10 cycles = 9 [OK]

Hint: Count max is one less than total cycles [OK]

Common Mistakes:

• Using clk'event instead of rising_edge(clk) (still valid but less modern)
• Checking reset after clock event
• Declaring tc as wrong type

5. You want to design a VHDL timer that counts from 0 to 15 and sets terminal count output tc high for exactly one clock cycle when count reaches 15. Which code snippet correctly implements this behavior?

hard

A. if count = 15 then
count <= 15;
tc <= '1';
else
count <= count + 1;
tc <= '0';
end if;

B. if count = 15 then
count <= 0;
tc <= '1';
else
count <= count + 1;
tc <= '0';
end if;

C. if count >= 15 then
tc <= '1';
else
count <= count + 1;
tc <= '0';
end if;

D. if count = 14 then
count <= 0;
tc <= '1';
else
count <= count + 1;
tc <= '0';
end if;

Solution

1. Step 1: Understand terminal count condition

   The timer must reset count to 0 and set tc='1' exactly when count = 15.

2. Step 2: Evaluate each option

   if count = 15 then count <= 0; tc <= '1'; else count <= count + 1; tc <= '0'; end if; resets count at 15 and sets tc='1' for one cycle. if count = 15 then count <= 15; tc <= '1'; else count <= count + 1; tc <= '0'; end if; holds count at 15, causing no reset. if count >= 15 then tc <= '1'; else count <= count + 1; tc <= '0'; end if; does not reset count, causing tc to remain high for multiple cycles. if count = 14 then count <= 0; tc <= '1'; else count <= count + 1; tc <= '0'; end if; triggers at 14, which is incorrect.

3. Final Answer:

   if count = 15 then count <= 0; tc <= '1'; else count <= count + 1; tc <= '0'; end if; -> Option B

4. Quick Check:

   tc high only at count = 15, then reset [OK]

Hint: Reset count and set tc only at exact max count [OK]

Common Mistakes:

• Not resetting count after terminal count
• Setting tc high for multiple cycles
• Triggering terminal count too early