Timer with terminal count output in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output signal value after 10 clock cycles?

Consider a VHDL timer counting from 0 to 9 with a terminal count output that goes high when the count reaches 9. What is the value of the terminal count output (tc) after 10 clock cycles?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity timer is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           tc : out STD_LOGIC);
end timer;

architecture Behavioral of timer is
    signal count : unsigned(3 downto 0) := (others => '0');
begin
    process(clk, reset)
    begin
        if reset = '1' then
            count <= (others => '0');
        elsif rising_edge(clk) then
            if count = 9 then
                count <= (others => '0');
            else
                count <= count + 1;
            end if;
        end if;
    end process;
    tc <= '1' when count = 9 else '0';
end Behavioral;

A Undefined (signal not stable)

B '1'

C '0'

D Signal toggles every clock cycle

💡 Hint

Think about when the terminal count output is set high in relation to the count value.

The terminal count output (tc) is assigned '1' when the count reaches 9. After 10 clock cycles, the count reaches 9 once, so tc is '1'.

❓ Predict Output

intermediate

What is the count value after reset is deasserted and 5 clock cycles?

Given the same timer design, what is the value of the count signal after reset is deasserted (reset = '0') and 5 rising clock edges?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity timer is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           count_out : out unsigned(3 downto 0));
end timer;

architecture Behavioral of timer is
    signal count : unsigned(3 downto 0) := (others => '0');
begin
    process(clk, reset)
    begin
        if reset = '1' then
            count <= (others => '0');
        elsif rising_edge(clk) then
            if count = 9 then
                count <= (others => '0');
            else
                count <= count + 1;
            end if;
        end if;
    end process;
    count_out <= count;
end Behavioral;

A 9

B 4

C 5

D 0

💡 Hint

Count increments by 1 each clock cycle after reset is released.

After reset is '0', the count starts at 0 and increments by 1 each clock cycle. After 5 cycles, count = 5.

🔧 Debug

advanced

Identify the error causing the terminal count output to never go high

In the following VHDL code, the terminal count output (tc) never goes high. What is the cause of this problem?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity timer is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           tc : out STD_LOGIC);
end timer;

architecture Behavioral of timer is
    signal count : unsigned(3 downto 0) := (others => '0');
begin
    process(clk, reset)
    begin
        if reset = '1' then
            count <= (others => '0');
        elsif rising_edge(clk) then
            if count = 10 then
                count <= (others => '0');
            else
                count <= count + 1;
            end if;
        end if;
    end process;
    tc <= '1' when count = 9 else '0';
end Behavioral;

A The count comparison uses 10, which is out of range for 4 bits, so count never equals 10

B The reset signal is asynchronous and causes glitches

C The terminal count output is assigned inside the process incorrectly

D The count signal is not initialized

💡 Hint

Check the maximum value a 4-bit unsigned signal can hold.

A 4-bit unsigned signal can only represent values 0 to 15, but the count is compared to 10 to reset. Since count increments from 0 to 9, it never reaches 10, so the reset condition never triggers and count never resets. This causes tc to never be '1' because count never equals 9 at the right time.

📝 Syntax

advanced

Which option causes a syntax error in the timer process?

Which of the following code snippets will cause a syntax error in the timer process?

A if reset = '1' then count <= (others => '0') elsif rising_edge(clk) then count <= count + 1; end if;

B if reset = '1' then count <= (others => '0'); elsif rising_edge(clk) then count <= count + 1; end if;

C ;fi dne ;1 + tnuoc =< tnuoc neht )klc(egde_gnisir fisle ;)'0' >= srehto( =< tnuoc neht '1' = teser fi

D if reset = '1' then count <= (others => '0'); elsif rising_edge(clk) then count <= count + 1; else null; end if;

💡 Hint

Look for missing semicolons or keywords in the if-elsif statement.

Option A is missing a semicolon after the first assignment, causing a syntax error. All other options have correct syntax.

🚀 Application

expert

How many clock cycles until terminal count output pulses high twice?

Given a timer counting from 0 to 9 with terminal count output (tc) going high when count = 9, how many clock cycles are needed for tc to pulse high twice starting from reset?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity timer is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           tc : out STD_LOGIC);
end timer;

architecture Behavioral of timer is
    signal count : unsigned(3 downto 0) := (others => '0');
begin
    process(clk, reset)
    begin
        if reset = '1' then
            count <= (others => '0');
        elsif rising_edge(clk) then
            if count = 9 then
                count <= (others => '0');
            else
                count <= count + 1;
            end if;
        end if;
    end process;
    tc <= '1' when count = 9 else '0';
end Behavioral;

A 21 clock cycles

B 20 clock cycles

C 18 clock cycles

D 19 clock cycles

💡 Hint

Count how many cycles it takes for the count to reach 9 twice starting from 0.

The count starts at 0 after reset. It takes 10 clock cycles to reach 9 the first time (counts 0 to 9). After resetting to 0, it takes 9 more cycles to reach 9 again. So total cycles = 10 + 9 = 19.

Practice

1. What does the terminal count output signal in a VHDL timer?

easy

A. The timer has reached its preset count value

B. The timer is reset to zero

C. The clock signal is inactive

D. The timer is paused

Solution

1. Step 1: Understand the timer function

   A timer counts clock pulses until it reaches a preset value.

2. Step 2: Define terminal count output meaning

   The terminal count output signals when the timer hits that preset value.

3. Final Answer:

   The timer has reached its preset count value -> Option A

4. Quick Check:

   Terminal count = timer reached preset [OK]

Hint: Terminal count means timer reached set value [OK]

Common Mistakes:

• Confusing terminal count with reset signal
• Thinking terminal count means timer stopped
• Mixing terminal count with clock inactivity

2. Which of the following is the correct VHDL syntax to declare a terminal count output signal named tc as a std_logic?

easy

A. signal tc std_logic;

B. signal tc : std_logic

C. signal tc : std_logic;

D. signal tc = std_logic;

Solution

1. Step 1: Recall VHDL signal declaration syntax

   Signals are declared with keyword 'signal', name, colon, type, and semicolon.

2. Step 2: Check each option

   signal tc : std_logic; uses correct syntax: 'signal tc : std_logic;'. Others miss colon or semicolon or use wrong assignment.

3. Final Answer:

   signal tc : std_logic; -> Option C

4. Quick Check:

   Signal declaration = signal name : type; [OK]

Hint: Signal declaration needs colon and semicolon [OK]

Common Mistakes:

• Omitting colon between name and type
• Forgetting semicolon at end
• Using equals sign instead of colon

3. Given this VHDL process for a timer:

process(clk, reset)
begin
  if reset = '1' then
    count <= 0;
    tc <= '0';
  elsif rising_edge(clk) then
    if count = 9 then
      count <= 0;
      tc <= '1';
    else
      count <= count + 1;
      tc <= '0';
    end if;
  end if;
end process;

What is the value of tc after 10 clock cycles without reset?

medium

A. '1' on the 10th cycle, '0' otherwise

B. '0' on all cycles

C. '1' on every cycle

D. '1' on the 9th cycle only

Solution

1. Step 1: Analyze counting and terminal count logic

   The counter counts from 0 to 9. When count = 9, tc is set to '1' and count resets to 0.

2. Step 2: Trace tc output over 10 clock cycles

   For cycles 1 to 9, tc = '0'. On the 10th cycle (count=9), tc = '1'. Then count resets.

3. Final Answer:

   '1' on the 10th cycle, '0' otherwise -> Option A

4. Quick Check:

   tc = '1' at terminal count (10th cycle) [OK]

Hint: tc is '1' only when count reaches max [OK]

Common Mistakes:

• Assuming tc is '1' every cycle
• Confusing count value for tc output
• Forgetting count resets after terminal count

4. Identify the error in this VHDL timer process:

process(clk, reset)
begin
  if reset = '1' then
    count <= 0;
    tc <= '0';
  elsif clk'event and clk = '1' then
    if count = 10 then
      count <= 0;
      tc <= '1';
    else
      count <= count + 1;
      tc <= '0';
    end if;
  end if;
end process;

medium

A. tc signal should be declared as integer

B. Using clk'event and clk = '1' instead of rising_edge(clk)

C. Reset condition should be checked after clock event

D. Count comparison should be count = 9, not 10

Solution

1. Step 1: Check count comparison logic

   The timer counts from 0, so max count for 10 cycles is 9, not 10.

2. Step 2: Understand effect of wrong count value

   If count = 10 is checked, terminal count never triggers because count resets at 9+1=10, causing off-by-one error.

3. Final Answer:

   Count comparison should be count = 9, not 10 -> Option D

4. Quick Check:

   Max count for 10 cycles = 9 [OK]

Hint: Count max is one less than total cycles [OK]

Common Mistakes:

• Using clk'event instead of rising_edge(clk) (still valid but less modern)
• Checking reset after clock event
• Declaring tc as wrong type

5. You want to design a VHDL timer that counts from 0 to 15 and sets terminal count output tc high for exactly one clock cycle when count reaches 15. Which code snippet correctly implements this behavior?

hard

A. if count = 15 then
count <= 15;
tc <= '1';
else
count <= count + 1;
tc <= '0';
end if;

B. if count = 15 then
count <= 0;
tc <= '1';
else
count <= count + 1;
tc <= '0';
end if;

C. if count >= 15 then
tc <= '1';
else
count <= count + 1;
tc <= '0';
end if;

D. if count = 14 then
count <= 0;
tc <= '1';
else
count <= count + 1;
tc <= '0';
end if;

Solution

1. Step 1: Understand terminal count condition

   The timer must reset count to 0 and set tc='1' exactly when count = 15.

2. Step 2: Evaluate each option

   if count = 15 then count <= 0; tc <= '1'; else count <= count + 1; tc <= '0'; end if; resets count at 15 and sets tc='1' for one cycle. if count = 15 then count <= 15; tc <= '1'; else count <= count + 1; tc <= '0'; end if; holds count at 15, causing no reset. if count >= 15 then tc <= '1'; else count <= count + 1; tc <= '0'; end if; does not reset count, causing tc to remain high for multiple cycles. if count = 14 then count <= 0; tc <= '1'; else count <= count + 1; tc <= '0'; end if; triggers at 14, which is incorrect.

3. Final Answer:

   if count = 15 then count <= 0; tc <= '1'; else count <= count + 1; tc <= '0'; end if; -> Option B

4. Quick Check:

   tc high only at count = 15, then reset [OK]

Hint: Reset count and set tc only at exact max count [OK]

Common Mistakes:

• Not resetting count after terminal count
• Setting tc high for multiple cycles
• Triggering terminal count too early