Process execution semantics in VHDL - Step-by-Step Execution

Concept Flow - Process execution semantics

Process starts

↓

Evaluate sensitivity list

↓

Wait for event on signals in sensitivity list

↓

Process triggered

↓

Execute sequential statements inside process

↓

Process suspends until next event

↩Back to wait for event

A VHDL process waits for changes on signals in its sensitivity list, then executes its statements sequentially, and suspends again until the next event.

Execution Sample

VHDL

process(clk, reset)
begin
  if reset = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

This process resets q to '0' when reset is high, otherwise on rising clock edge it assigns d to q.

Execution Table

Step	Event	Condition Evaluated	Action Taken	Signal q Value
1	reset='1' event	reset = '1' is True	q <= '0'	'0'
2	clk rising edge event	reset = '1' is False	q <= d	d's value
3	clk falling edge event	No rising edge	No action	unchanged
4	No event	Process suspended	No action	unchanged

💡 Process suspends waiting for next event on clk or reset signals

Variable Tracker

Signal/Variable	Start	After Step 1	After Step 2	After Step 3	Final
q	undefined	'0'	d's value	d's value	d's value or '0' depending on events

Key Moments - 3 Insights

Why does the process only run when signals in the sensitivity list change?

Because the process is triggered only by events on signals in its sensitivity list, as shown in execution_table step 1 and 2 where events on reset and clk cause execution.

What happens inside the process between events?

The process suspends and does not execute any statements until a new event occurs, as shown in step 4 where no event means no action.

Why does q keep its value when no event happens?

Because signal assignments inside the process only happen during execution triggered by events, so q remains unchanged between events (step 3 and 4).

Visual Quiz - 3 Questions

Look at the execution table, what is the value of q after step 1?

A '0'

B d's value

C unchanged

D undefined

💡 Hint

Check the 'Signal q Value' column in row for step 1.

At which step does the process suspend waiting for the next event?

A Step 2

B Step 3

C Step 4

D Step 1

💡 Hint

Look for the row where the action is 'No action' and the process is suspended.

If the sensitivity list did not include reset, what would happen at step 1?

A Process would still execute and reset q

B Process would not execute on reset event

C Process would execute on any signal change

D Process would execute continuously

💡 Hint

Sensitivity list controls which signals trigger the process, see concept_flow and execution_table steps.

Concept Snapshot

VHDL process executes sequential statements only when signals in its sensitivity list change.
It suspends between events, waiting for triggers.
Inside, signal assignments happen sequentially.
Sensitivity list controls when process wakes up.
Process models hardware behavior reacting to signal changes.

Full Transcript

In VHDL, a process waits for changes on signals listed in its sensitivity list. When one of these signals changes, the process wakes up and runs its sequential statements. For example, if reset is high, the process sets q to zero. If there is a rising clock edge, it assigns d to q. Between these events, the process suspends and does nothing, so q keeps its value. This behavior models hardware that reacts only when inputs change, making simulation efficient and accurate.

Practice

1. What happens when a signal in a VHDL process's sensitivity list changes?

easy

A. The entire process executes from the beginning once.

B. Only the changed signal is updated inside the process.

C. The process pauses until the signal stabilizes.

D. The process executes partially based on the changed signal.

Solution

1. Step 1: Understand sensitivity list trigger

   In VHDL, a process runs fully whenever any signal in its sensitivity list changes.

2. Step 2: Execution behavior

   The process does not partially run or pause; it executes all statements sequentially from the start.

3. Final Answer:

   The entire process executes from the beginning once. -> Option A

4. Quick Check:

   Process runs fully on sensitivity change = A [OK]

Hint: Process runs fully on any sensitivity list signal change [OK]

Common Mistakes:

• Thinking only changed signals update inside process
• Believing process pauses or partially runs
• Confusing process with concurrent statements

2. Which of the following is the correct syntax to declare a process with signals clk and reset in its sensitivity list?

easy

A. process(clk reset) begin ... end process;

B. process begin clk, reset; ... end process;

C. process(clk; reset) begin ... end process;

D. process(clk, reset) begin ... end process;

Solution

1. Step 1: Check sensitivity list syntax

   The sensitivity list must be inside parentheses, with signals separated by commas.

2. Step 2: Validate options

   process(clk, reset) begin ... end process; uses correct syntax: process(clk, reset) begin ... end process; Options A, B, and D have syntax errors (missing commas, wrong separators).

3. Final Answer:

   process(clk, reset) begin ... end process; -> Option D

4. Quick Check:

   Correct sensitivity list syntax uses commas = C [OK]

Hint: Use commas between signals in sensitivity list parentheses [OK]

Common Mistakes:

• Omitting commas between signals
• Using semicolons instead of commas
• Placing signals outside parentheses

3. Given the following VHDL process:

process(clk)
begin
  if rising_edge(clk) then
    count <= count + 1;
  end if;
end process;

What happens to count when clk changes from '0' to '1'?

medium

A. Process causes a syntax error.

B. count resets to 0.

C. count increments by 1.

D. count remains unchanged.

Solution

1. Step 1: Identify trigger condition

   The process triggers on any change of clk. The if rising_edge(clk) checks for a 0 to 1 transition.

2. Step 2: Effect on count

   When clk rises, count increments by 1 as per the assignment.

3. Final Answer:

   count increments by 1. -> Option C

4. Quick Check:

   Rising edge triggers increment = D [OK]

Hint: Rising edge on clk triggers count increment [OK]

Common Mistakes:

• Confusing rising_edge with falling_edge
• Assuming count resets instead of increments
• Thinking process syntax is incorrect

4. Consider this VHDL process:

process(clk)
begin
  if clk = '1' then
    signal_a <= '0';
  else
    signal_a <= '1';
  end if;
end process;

What is the main problem with this process?

medium

A. It will cause a syntax error due to missing sensitivity signals.

B. It may create a latch because it lacks a clock edge condition.

C. It will never execute because clk is not in sensitivity list.

D. It updates signal_a asynchronously, which is always correct.

Solution

1. Step 1: Analyze sensitivity list and conditions

   The process triggers on any clk change, but uses level check (clk = '1') instead of edge detection.

2. Step 2: Understand latch creation

   Because assignments depend on clk level without edge detection, synthesis tools may infer a latch to hold signal_a's value.

3. Final Answer:

   It may create a latch because it lacks a clock edge condition. -> Option B

4. Quick Check:

   Level check without edge causes latch = B [OK]

Hint: Use rising_edge or falling_edge to avoid latches [OK]

Common Mistakes:

• Assuming missing sensitivity signals cause syntax error
• Thinking process won't execute without edge
• Believing asynchronous updates are always safe

5. You want to design a VHDL process that increments a counter only on the rising edge of clk and asynchronously resets it to zero when reset is '1'. Which process structure correctly implements this behavior?

hard

A. process(clk, reset)
begin
if reset = '1' then
count <= 0;
elsif rising_edge(clk) then
count <= count + 1;
end if;
end process;

B. process(clk)
begin
if reset = '1' then
count <= 0;
elsif rising_edge(clk) then
count <= count + 1;
end if;
end process;

C. process(reset)
begin
if reset = '1' then
count <= 0;
elsif rising_edge(clk) then
count <= count + 1;
end if;
end process;

D. process(clk, reset)
begin
if rising_edge(clk) then
if reset = '1' then
count <= 0;
else
count <= count + 1;
end if;
end if;
end process;

Solution

1. Step 1: Identify asynchronous reset

   Asynchronous reset requires reset in sensitivity list and checked before clock edge.

2. Step 2: Check process structure

   process(clk, reset)
   begin
     if reset = '1' then
       count <= 0;
     elsif rising_edge(clk) then
       count <= count + 1;
     end if;
   end process;

   checks reset = '1' first, then rising_edge(clk), correctly implementing async reset and sync count increment.

3. Step 3: Validate other options

   process(clk)
   begin
     if reset = '1' then
       count <= 0;
     elsif rising_edge(clk) then
       count <= count + 1;
     end if;
   end process;

   misses reset in sensitivity list (wrong for async reset).

   process(reset)
   begin
     if reset = '1' then
       count <= 0;
     elsif rising_edge(clk) then
       count <= count + 1;
     end if;
   end process;

   triggers only on reset, ignoring clk.

   process(clk, reset)
   begin
     if rising_edge(clk) then
       if reset = '1' then
         count <= 0;
       else
         count <= count + 1;
       end if;
     end if;
   end process;

   treats reset synchronously inside clock edge.

4. Final Answer:

   process(clk, reset) begin if reset = '1' then count <= 0; elsif rising_edge(clk) then count <= count + 1; end if; end process; -> Option A

5. Quick Check:

   Async reset checked first with reset in sensitivity list = A [OK]

Hint: Put async reset first and include it in sensitivity list [OK]

Common Mistakes:

• Omitting reset from sensitivity list for async reset
• Checking reset inside clock edge (sync reset)
• Using wrong sensitivity list signals