Process execution semantics in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a process that triggers on a clock signal.

VHDL

process([1])
begin
  if rising_edge(clk) then
    -- process body
  end if;
end process;

Drag options to blanks, or click blank then click option'

Aclk

Breset

Cclk'event

Dclk and reset

Attempts:

3 left

💡 Hint

Common Mistakes

Using clk'event in the sensitivity list, as it is an attribute not a signal.

Including unrelated signals in the sensitivity list.

The process sensitivity list must include clk to be sensitive to clock signal changes. The rising_edge(clk) inside detects the rising edge.

2fill in blank

medium

Complete the code to check for a rising edge on the clock inside the process.

VHDL

if [1](clk) then
  -- synchronous logic
end if;

Drag options to blanks, or click blank then click option'

Aclk'event

Bfalling_edge

Crising_edge

Dclk = '1'

Attempts:

3 left

💡 Hint

Common Mistakes

Using falling_edge instead of rising_edge.

Checking clk = '1' without edge detection.

The rising_edge(clk) function checks for a rising clock edge.

3fill in blank

hard

Fix the error in the process sensitivity list to correctly trigger on clock and reset signals.

VHDL

process([1])
begin
  if reset = '1' then
    -- reset logic
  elsif rising_edge(clk) then
    -- main logic
  end if;
end process;

Drag options to blanks, or click blank then click option'

Aclk, reset

Bclk and reset

Cclk or reset

Dclk reset

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'and' or 'or' instead of commas.

Listing signals without any separator.

The sensitivity list must list signals separated by commas: clk, reset.

4fill in blank

hard

Fill both blanks to create a process that triggers on clock and asynchronous reset signals.

VHDL

process([1], [2])
begin
  if reset = '1' then
    -- reset logic
  elsif rising_edge(clk) then
    -- main logic
  end if;
end process;

Drag options to blanks, or click blank then click option'

Aclk

Breset

Cclk'event

Dreset'event

Attempts:

3 left

💡 Hint

Common Mistakes

Using event attributes in the sensitivity list.

Using logical operators instead of commas.

The sensitivity list should include the signals clk and reset separated by a comma.

5fill in blank

hard

Fill all three blanks to define a process with sensitivity list and conditional checks for reset and clock edges.

VHDL

process([1], [2])
begin
  if [3] = '1' then
    -- reset logic
  elsif rising_edge(clk) then
    -- main logic
  end if;
end process;

Drag options to blanks, or click blank then click option'

Aclk

Breset

Dclk'event

Attempts:

3 left

💡 Hint

Common Mistakes

Using event attributes in sensitivity list or reset condition.

Mixing signal names and event attributes incorrectly.

The sensitivity list includes clk and reset. The reset condition checks if reset = '1'.

Practice

1. What happens when a signal in a VHDL process's sensitivity list changes?

easy

A. The entire process executes from the beginning once.

B. Only the changed signal is updated inside the process.

C. The process pauses until the signal stabilizes.

D. The process executes partially based on the changed signal.

Solution

1. Step 1: Understand sensitivity list trigger

   In VHDL, a process runs fully whenever any signal in its sensitivity list changes.

2. Step 2: Execution behavior

   The process does not partially run or pause; it executes all statements sequentially from the start.

3. Final Answer:

   The entire process executes from the beginning once. -> Option A

4. Quick Check:

   Process runs fully on sensitivity change = A [OK]

Hint: Process runs fully on any sensitivity list signal change [OK]

Common Mistakes:

• Thinking only changed signals update inside process
• Believing process pauses or partially runs
• Confusing process with concurrent statements

2. Which of the following is the correct syntax to declare a process with signals clk and reset in its sensitivity list?

easy

A. process(clk reset) begin ... end process;

B. process begin clk, reset; ... end process;

C. process(clk; reset) begin ... end process;

D. process(clk, reset) begin ... end process;

Solution

1. Step 1: Check sensitivity list syntax

   The sensitivity list must be inside parentheses, with signals separated by commas.

2. Step 2: Validate options

   process(clk, reset) begin ... end process; uses correct syntax: process(clk, reset) begin ... end process; Options A, B, and D have syntax errors (missing commas, wrong separators).

3. Final Answer:

   process(clk, reset) begin ... end process; -> Option D

4. Quick Check:

   Correct sensitivity list syntax uses commas = C [OK]

Hint: Use commas between signals in sensitivity list parentheses [OK]

Common Mistakes:

• Omitting commas between signals
• Using semicolons instead of commas
• Placing signals outside parentheses

3. Given the following VHDL process:

process(clk)
begin
  if rising_edge(clk) then
    count <= count + 1;
  end if;
end process;

What happens to count when clk changes from '0' to '1'?

medium

A. Process causes a syntax error.

B. count resets to 0.

C. count increments by 1.

D. count remains unchanged.

Solution

1. Step 1: Identify trigger condition

   The process triggers on any change of clk. The if rising_edge(clk) checks for a 0 to 1 transition.

2. Step 2: Effect on count

   When clk rises, count increments by 1 as per the assignment.

3. Final Answer:

   count increments by 1. -> Option C

4. Quick Check:

   Rising edge triggers increment = D [OK]

Hint: Rising edge on clk triggers count increment [OK]

Common Mistakes:

• Confusing rising_edge with falling_edge
• Assuming count resets instead of increments
• Thinking process syntax is incorrect

4. Consider this VHDL process:

process(clk)
begin
  if clk = '1' then
    signal_a <= '0';
  else
    signal_a <= '1';
  end if;
end process;

What is the main problem with this process?

medium

A. It will cause a syntax error due to missing sensitivity signals.

B. It may create a latch because it lacks a clock edge condition.

C. It will never execute because clk is not in sensitivity list.

D. It updates signal_a asynchronously, which is always correct.

Solution

1. Step 1: Analyze sensitivity list and conditions

   The process triggers on any clk change, but uses level check (clk = '1') instead of edge detection.

2. Step 2: Understand latch creation

   Because assignments depend on clk level without edge detection, synthesis tools may infer a latch to hold signal_a's value.

3. Final Answer:

   It may create a latch because it lacks a clock edge condition. -> Option B

4. Quick Check:

   Level check without edge causes latch = B [OK]

Hint: Use rising_edge or falling_edge to avoid latches [OK]

Common Mistakes:

• Assuming missing sensitivity signals cause syntax error
• Thinking process won't execute without edge
• Believing asynchronous updates are always safe

5. You want to design a VHDL process that increments a counter only on the rising edge of clk and asynchronously resets it to zero when reset is '1'. Which process structure correctly implements this behavior?

hard

A. process(clk, reset)
begin
if reset = '1' then
count <= 0;
elsif rising_edge(clk) then
count <= count + 1;
end if;
end process;

B. process(clk)
begin
if reset = '1' then
count <= 0;
elsif rising_edge(clk) then
count <= count + 1;
end if;
end process;

C. process(reset)
begin
if reset = '1' then
count <= 0;
elsif rising_edge(clk) then
count <= count + 1;
end if;
end process;

D. process(clk, reset)
begin
if rising_edge(clk) then
if reset = '1' then
count <= 0;
else
count <= count + 1;
end if;
end if;
end process;

Solution

1. Step 1: Identify asynchronous reset

   Asynchronous reset requires reset in sensitivity list and checked before clock edge.

2. Step 2: Check process structure

   process(clk, reset)
   begin
     if reset = '1' then
       count <= 0;
     elsif rising_edge(clk) then
       count <= count + 1;
     end if;
   end process;

   checks reset = '1' first, then rising_edge(clk), correctly implementing async reset and sync count increment.

3. Step 3: Validate other options

   process(clk)
   begin
     if reset = '1' then
       count <= 0;
     elsif rising_edge(clk) then
       count <= count + 1;
     end if;
   end process;

   misses reset in sensitivity list (wrong for async reset).

   process(reset)
   begin
     if reset = '1' then
       count <= 0;
     elsif rising_edge(clk) then
       count <= count + 1;
     end if;
   end process;

   triggers only on reset, ignoring clk.

   process(clk, reset)
   begin
     if rising_edge(clk) then
       if reset = '1' then
         count <= 0;
       else
         count <= count + 1;
       end if;
     end if;
   end process;

   treats reset synchronously inside clock edge.

4. Final Answer:

   process(clk, reset) begin if reset = '1' then count <= 0; elsif rising_edge(clk) then count <= count + 1; end if; end process; -> Option A

5. Quick Check:

   Async reset checked first with reset in sensitivity list = A [OK]

Hint: Put async reset first and include it in sensitivity list [OK]

Common Mistakes:

• Omitting reset from sensitivity list for async reset
• Checking reset inside clock edge (sync reset)
• Using wrong sensitivity list signals