Process execution semantics in VHDL - Mini Project: Build & Apply

Understanding Process Execution Semantics in VHDL

📖 Scenario: You are designing a simple digital circuit using VHDL. You want to understand how processes execute and how signals update inside a process block.

🎯 Goal: Build a VHDL process that models a simple signal assignment and observe how the process executes and updates signals.

📋 What You'll Learn

Create a signal called clk of type std_logic.

Create a signal called counter of type integer initialized to 0.

Create a process sensitive to clk that increments counter by 1 on each rising edge of clk.

Print the value of counter after the process executes.

💡 Why This Matters

🌍 Real World

Understanding process execution is essential for designing reliable digital circuits and systems using VHDL.

💼 Career

Knowledge of process execution semantics is crucial for FPGA and ASIC design engineers to write correct and efficient hardware descriptions.

1

DATA SETUP: Declare signals

Declare a signal called clk of type std_logic initialized to '0', and a signal called counter of type integer initialized to 0 inside the architecture.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity simple_counter is
    Port ();
end simple_counter;

architecture Behavioral of simple_counter is
    -- Declare clk and counter signals here
    -- Your code here
begin

end Behavioral;

Hint

Use signal clk : std_logic := '0'; and signal counter : integer := 0; inside the architecture declaration section.

2

CONFIGURATION: Create a clock process

Add a process called clock_process that toggles the clk signal every 10 ns using a wait statement.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity simple_counter is
    Port ();
end simple_counter;

architecture Behavioral of simple_counter is
    signal clk : std_logic := '0';
    signal counter : integer := 0;
begin
    -- Create clock_process to toggle clk every 10 ns
    -- Your code here
end Behavioral;

Hint

Use a process without sensitivity list and toggle clk with wait for 10 ns; delays.

3

CORE LOGIC: Create counter process with rising edge detection

Add a process called counter_process sensitive to clk that increments counter by 1 on the rising edge of clk using if rising_edge(clk).

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity simple_counter is
    Port ();
end simple_counter;

architecture Behavioral of simple_counter is
    signal clk : std_logic := '0';
    signal counter : integer := 0;
begin
    clock_process : process
    begin
        clk <= '0';
        wait for 10 ns;
        clk <= '1';
        wait for 10 ns;
    end process clock_process;

    -- Create counter_process sensitive to clk
    -- Your code here
end Behavioral;

Hint

Use process(clk) and inside it check if rising_edge(clk) then to increment counter.

4

OUTPUT: Display counter value in simulation

Add a process called monitor_process sensitive to counter that prints the current value of counter using report statement.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity simple_counter is
    Port ();
end simple_counter;

architecture Behavioral of simple_counter is
    signal clk : std_logic := '0';
    signal counter : integer := 0;
begin
    clock_process : process
    begin
        clk <= '0';
        wait for 10 ns;
        clk <= '1';
        wait for 10 ns;
    end process clock_process;

    counter_process : process(clk)
    begin
        if rising_edge(clk) then
            counter <= counter + 1;
        end if;
    end process counter_process;

    -- Create monitor_process sensitive to counter
    -- Your code here
end Behavioral;

Hint

Use a process sensitive to counter and inside it use report to print the counter value.

Practice

1. What happens when a signal in a VHDL process's sensitivity list changes?

easy

A. The entire process executes from the beginning once.

B. Only the changed signal is updated inside the process.

C. The process pauses until the signal stabilizes.

D. The process executes partially based on the changed signal.

Solution

1. Step 1: Understand sensitivity list trigger

   In VHDL, a process runs fully whenever any signal in its sensitivity list changes.

2. Step 2: Execution behavior

   The process does not partially run or pause; it executes all statements sequentially from the start.

3. Final Answer:

   The entire process executes from the beginning once. -> Option A

4. Quick Check:

   Process runs fully on sensitivity change = A [OK]

Hint: Process runs fully on any sensitivity list signal change [OK]

Common Mistakes:

• Thinking only changed signals update inside process
• Believing process pauses or partially runs
• Confusing process with concurrent statements

2. Which of the following is the correct syntax to declare a process with signals clk and reset in its sensitivity list?

easy

A. process(clk reset) begin ... end process;

B. process begin clk, reset; ... end process;

C. process(clk; reset) begin ... end process;

D. process(clk, reset) begin ... end process;

Solution

1. Step 1: Check sensitivity list syntax

   The sensitivity list must be inside parentheses, with signals separated by commas.

2. Step 2: Validate options

   process(clk, reset) begin ... end process; uses correct syntax: process(clk, reset) begin ... end process; Options A, B, and D have syntax errors (missing commas, wrong separators).

3. Final Answer:

   process(clk, reset) begin ... end process; -> Option D

4. Quick Check:

   Correct sensitivity list syntax uses commas = C [OK]

Hint: Use commas between signals in sensitivity list parentheses [OK]

Common Mistakes:

• Omitting commas between signals
• Using semicolons instead of commas
• Placing signals outside parentheses

3. Given the following VHDL process:

process(clk)
begin
  if rising_edge(clk) then
    count <= count + 1;
  end if;
end process;

What happens to count when clk changes from '0' to '1'?

medium

A. Process causes a syntax error.

B. count resets to 0.

C. count increments by 1.

D. count remains unchanged.

Solution

1. Step 1: Identify trigger condition

   The process triggers on any change of clk. The if rising_edge(clk) checks for a 0 to 1 transition.

2. Step 2: Effect on count

   When clk rises, count increments by 1 as per the assignment.

3. Final Answer:

   count increments by 1. -> Option C

4. Quick Check:

   Rising edge triggers increment = D [OK]

Hint: Rising edge on clk triggers count increment [OK]

Common Mistakes:

• Confusing rising_edge with falling_edge
• Assuming count resets instead of increments
• Thinking process syntax is incorrect

4. Consider this VHDL process:

process(clk)
begin
  if clk = '1' then
    signal_a <= '0';
  else
    signal_a <= '1';
  end if;
end process;

What is the main problem with this process?

medium

A. It will cause a syntax error due to missing sensitivity signals.

B. It may create a latch because it lacks a clock edge condition.

C. It will never execute because clk is not in sensitivity list.

D. It updates signal_a asynchronously, which is always correct.

Solution

1. Step 1: Analyze sensitivity list and conditions

   The process triggers on any clk change, but uses level check (clk = '1') instead of edge detection.

2. Step 2: Understand latch creation

   Because assignments depend on clk level without edge detection, synthesis tools may infer a latch to hold signal_a's value.

3. Final Answer:

   It may create a latch because it lacks a clock edge condition. -> Option B

4. Quick Check:

   Level check without edge causes latch = B [OK]

Hint: Use rising_edge or falling_edge to avoid latches [OK]

Common Mistakes:

• Assuming missing sensitivity signals cause syntax error
• Thinking process won't execute without edge
• Believing asynchronous updates are always safe

5. You want to design a VHDL process that increments a counter only on the rising edge of clk and asynchronously resets it to zero when reset is '1'. Which process structure correctly implements this behavior?

hard

A. process(clk, reset)
begin
if reset = '1' then
count <= 0;
elsif rising_edge(clk) then
count <= count + 1;
end if;
end process;

B. process(clk)
begin
if reset = '1' then
count <= 0;
elsif rising_edge(clk) then
count <= count + 1;
end if;
end process;

C. process(reset)
begin
if reset = '1' then
count <= 0;
elsif rising_edge(clk) then
count <= count + 1;
end if;
end process;

D. process(clk, reset)
begin
if rising_edge(clk) then
if reset = '1' then
count <= 0;
else
count <= count + 1;
end if;
end if;
end process;

Solution

1. Step 1: Identify asynchronous reset

   Asynchronous reset requires reset in sensitivity list and checked before clock edge.

2. Step 2: Check process structure

   process(clk, reset)
   begin
     if reset = '1' then
       count <= 0;
     elsif rising_edge(clk) then
       count <= count + 1;
     end if;
   end process;

   checks reset = '1' first, then rising_edge(clk), correctly implementing async reset and sync count increment.

3. Step 3: Validate other options

   process(clk)
   begin
     if reset = '1' then
       count <= 0;
     elsif rising_edge(clk) then
       count <= count + 1;
     end if;
   end process;

   misses reset in sensitivity list (wrong for async reset).

   process(reset)
   begin
     if reset = '1' then
       count <= 0;
     elsif rising_edge(clk) then
       count <= count + 1;
     end if;
   end process;

   triggers only on reset, ignoring clk.

   process(clk, reset)
   begin
     if rising_edge(clk) then
       if reset = '1' then
         count <= 0;
       else
         count <= count + 1;
       end if;
     end if;
   end process;

   treats reset synchronously inside clock edge.

4. Final Answer:

   process(clk, reset) begin if reset = '1' then count <= 0; elsif rising_edge(clk) then count <= count + 1; end if; end process; -> Option A

5. Quick Check:

   Async reset checked first with reset in sensitivity list = A [OK]

Hint: Put async reset first and include it in sensitivity list [OK]

Common Mistakes:

• Omitting reset from sensitivity list for async reset
• Checking reset inside clock edge (sync reset)
• Using wrong sensitivity list signals